Senior Static Timing Design Manager - SoC & AI Processors

NXP Semiconductors NV; Austin (TX); On-site; USD 180,000 - 260,000; Full time

Job summary

NXP Semiconductors NV in Austin seeks a Static Timing Design Manager to lead a team of engineers focused on STA for MPU SoCs. You will develop, implement and verify timing constraints, drive timing closure at subsystem and full-chip levels, and collaborate with RTL/IP teams to fix timing issues in AI, Edge and automotive processors.

This role requires deep knowledge of timing flows, place & route, floorplanning, and cross-functional leadership across global design teams.

Qualifications

• BS or MS in Electrical or Computer Engineering.
• 15+ years of Physical Design experience for complex SoCs.
• Experience with STA Lead roles (≥3 years).
• Excellent communication skills, both oral and written.
• Experience with AI/agents in STA & PD domains.

Responsibilities

• Develop, implement and verify STA constraints.
• Efficient closure of Subsystem and SoC-level timing.
• Collaborate with RTL and IP design teams for timing fixes.
• Contribute to timing flow and methodology improvements.
• Collaborate with global design team to complete large SoC projects.
• Partner with Architecture and RTL teams to influence early design decisions.
• Coordinate with RTL, DV, DFT, EDA vendors while setting technical direction for the team.
• Work with methodology teams to continuously improve flows and processes.

Skills

STA Lead

Timing analysis

Verilog

RTL collaboration

Communication skills

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree in Electrical or Computer Engineering

Tools

EDA Tools

Place & Route

Floorplanning

Job description

NXP Semiconductors NV in Austin seeks a Static Timing Design Manager to lead a team of engineers focused on STA for MPU SoCs. You will develop, implement and verify timing constraints, drive timing closure at subsystem and full-chip levels, and collaborate with RTL/IP teams to fix timing issues in AI, Edge and automotive processors.

This role requires deep knowledge of timing flows, place & route, floorplanning, and cross-functional leadership across global design teams.