Senior STA Engineer – SoC Timing (3nm/5nm)

Arm; Austin (TX); Hybrid; USD 198,000 - 268,000; Full time

Benefits offered by this job

Hybrid work model

Recruitment accommodations

Job summary

Arm in Austin, TX is seeking a senior timing closure engineer to own chip and block level timing closure across complex multi-instantiated designs on leading-edge 5nm/3nm nodes. You will drive ECOs, manage constraints, and coordinate with EDA teams.

You will collaborate with silicon teams, handle functional/test-mode timing, and ensure IO interfaces and SOC bus protocols are properly implemented. This role offers a hybrid work model and a competitive salary.

Qualifications

• 6+ years of experience in timing convergence.
• Experience with industry standard STA tools and methodologies.
• Knowledge of timing corners, modes including DFT, process variations and signal integrity.
• Experience in timing closure for multi power domain designs.
• Collaborating across silicon engineering teams and with EDA vendors.
• Worked on constraints development and timing closure for 5nm or 3nm technologies.
• Strong automation (Perl/Python/TCL) and communication skills.

Responsibilities

• Own full chip and block level timing closure throughout the project cycle.
• Handle timing constraints for functional and test mode at different hierarchical levels.
• Work closely with multi-functional teams on resolving timing issues for major SOC blocks.
• ECO generation at both block and top level, coordinating timing/functional ECOs.
• Familiarity with IO interfaces and SOC bus protocols.

Skills

Timing convergence

STA tools

Timing corners & DFT

Multi-power-domain timing

Cross-team collaboration

Constraints development

Automation (Perl/Python/TCL)

Education

Masters or equivalent

Tools

Perl

Python

TCL

Job description

Arm in Austin, TX is seeking a senior timing closure engineer to own chip and block level timing closure across complex multi-instantiated designs on leading-edge 5nm/3nm nodes. You will drive ECOs, manage constraints, and coordinate with EDA teams.

You will collaborate with silicon teams, handle functional/test-mode timing, and ensure IO interfaces and SOC bus protocols are properly implemented. This role offers a hybrid work model and a competitive salary.