Low Power Design/Methodology Engineer

Qualcomm; San Diego (CA); On-site; USD 115,600 - 173,400; Full time

Benefits offered by this job

Competitive annual discretionary bonus

Opportunity for annual RSU grants

Highly competitive benefits package

Job summary

Qualcomm is seeking a skilled ASIC Designer to focus on adaptive power management solutions in San Diego, California. You will conduct RTL design, simulation, and verification, ensuring high-performance power management in its wireless SoC products.

The ideal candidate will have 3+ years of low power digital ASIC design experience, be familiar with scripting languages, and possess strong analytical skills in electrical engineering. Competitive pay and benefits are part of the package.

Qualifications

• 3 years of experience in low power digital ASIC design.
• Familiar with ASIC front-end design process.
• Proficiency in Verilog/System Verilog coding and scripting languages.

Responsibilities

• Design adaptive power management controller.
• Perform RTL design and verification for IP blocks.
• Work closely with teams to complete the IP design implementation.

Skills

Low power ASIC design

RTL coding

Scripting (Python, Perl, TCL)

Circuit analysis

SoC architecture understanding

Education

Masters or PhD in Electrical or Computer Engineering

Tools

Verilog/System Verilog

UPF

Power aware DV

Job description

Company: Qualcomm Technologies, Inc.

Job Overview

• Design adaptive power management controller, on-chip sensor controller and digital power meter.
• Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks.
• Work closely with technology/circuit design team to close IP block specification/requirement.
• Work closely with verification/physical design team to complete the IP design implementation.
• Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows.
• Work closely with system/software/test team to enable the low power feature in wireless SoC product.
• Work closely with system/software/test team to enable functional safety feature in automotive SoC product.
• Create/Enhance low power methodologies covering entire design cycle from RTL to GDS. Analyze how a new methodology will affect different phases of the design/verification cycle and work on fixing any issues.
• Provide feedback for low-power chip and system architecture.
• Understand and perform block & chip-level power analysis.
• Understand and create block-level power models.

Required for this Role

• 3 years of experience doing low power digital ASIC design.
• Familiar with ASIC front-end design process and related flow, including u-arch, RTL coding, simulation, synthesis, STA.
• Familiar with scripting languages like Python, Perl, TCL.
• Understanding of electrical engineering concepts, circuit analysis and logic design skills.

Preferred Qualifications

• Previous experience in AVS (adaptive voltage scaling) desired.
• Familiarity with advanced low power techniques and tools such as UPF, CLP, power aware DV and high speed clocking desired.
• Proficiency in Verilog/System Verilog coding, verification techniques, and scripting language, such as: Perl, Python, Tcl, and Make etc.
• Good understanding of SoC architecture/micro-architecture.
• Understanding of automotive functional safety standard ISO 26262 and analysis technique (FMEA/FMEDA) is a plus.
• Strong debugging capabilities at simulation, emulation, and Silicon environments, including ability to design interesting debug experiments.
• Collaborate closely with cross-function team to research, design and implement performance and power management strategy for product roadmap.

Education

• Masters or PhD in Electrical or Computer Engineering.

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• OR Master’s degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• OR PhD in Science, Engineering, or related field.

Pay range and Other Compensation & Benefits

• $115,600.00 - $173,400.00
• Competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).
• Highly competitive benefits package designed to support your success at work, at home, and at play.

EEO Employer

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.