SoC Physical Design Engineer: Netlist-to-Tapeout Impact

Apple Inc.; Austin, Northern (TX, KY); Hybrid; USD 110,000 - 150,000; Full time

Job summary

Apple Inc. in Austin, TX is seeking a Physical Design engineer to drive the netlist-to-tapeout flow for complex SOC partitions. You will collaborate with architecture, CAD, timing and logic design teams to meet schedule and design goals.

Responsibilities include timing, physical and electrical verification, GDS2 implementation, and driving signoff closure while continually improving design flows and addressing issues across the partitioning process.

Qualifications

• BS degree with 0+ years experience
• Basic understanding of logic gates
• Internship/co-op or coursework in computer architecture or VLSI preferred
• Ability to collaborate across multiple teams

Responsibilities

• Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals
• Conduct timing, physical and electrical verification and drive signoff closure
• Resolve and improve design and flow issues related to physical design
• Collaborate with architecture, CAD, timing and logic teams early in the design cycle

Skills

Verilog

VHDL

Python

Perl

TCL

SPICE

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Netlist to GDS2 flow

Floor-planning

Job description

Apple Inc. in Austin, TX is seeking a Physical Design engineer to drive the netlist-to-tapeout flow for complex SOC partitions. You will collaborate with architecture, CAD, timing and logic design teams to meet schedule and design goals.

Responsibilities include timing, physical and electrical verification, GDS2 implementation, and driving signoff closure while continually improving design flows and addressing issues across the partitioning process.