SoC Physical Design Engineer, PnR at Apple Inc. Austin, TX

Apple Inc.; Austin (TX); On-site; USD 150,000 - 230,000; Full time

Job summary

Apple Inc. in Austin, TX seeks a seasoned SoC Physical Design Engineer to lead PD efforts for high-performance, low-power designs. You will drive RTL-to-GDSII implementation, PnR, STA, and sign-off, while guiding design rules and methodologies with cross-functional teams.

The role requires deep PD expertise, a track record of tapeouts, and the ability to meet tight schedules on large SOCs (>20M gates) at >1GHz. Join a collaborative, engineering-focused environment.

Qualifications

• BS degree required with 10+ years in physical design or related field.
• Experience with high-performance, low-power PD for large SOCs.
• Strong ability to lead cross-functional PD initiatives.

Responsibilities

• Own RTL2GDSII PD implementation from RTL to GDSII and PnR.
• Lead timing closure, STA, EMIR, and sign-off activities.
• Develop guidelines, checklists, and best-known methods for PD.

Skills

Floorplanning

Timing closure

Power optimization

Physical verification

PD architecture

RTL2GDS

Education

BS degree

Tools

Industry standard PD tools

Job description

SoC Physical Design Engineer, PnR job at Apple Inc.. Austin, TX. We are seeking a seasoned Physical Design technical leader with deep expertise in high-performance & low-power design. In this highly visible role, you will work closely with cross-functional teams to come up with efficient chip and IP physical architecture taking into account physical design constraints early in the design cycle.

Description

• You will be responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off.
• You will also collaborate to drive methodologies and "best-known methods" to streamline PD work and develop guidelines and checklists.
• You will be the primary technical contact for your focus area and are motivated to solve more challenging timing closure issues, area & power optimization etc.

Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience.

Preferred Qualifications

• Knowledgeable in partition level P&R implementation including floorplanning, clock & power distribution, timing closure, and physical & electrical verification.
• Knowledge of PD construction & analysis flows and methodology.
• Strong interpersonal skills.
• Recent successful tapeouts in deep submicron technology.
• Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ.
• Shown ability to execute to stringent schedule & die size requirements.
• Experienced in industry standard tools and understanding their capabilities and underlying algorithms.

• Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.