Senior SoC Physical Design Lead (High-Perf / Low-Power)

Apple Inc.; Austin (TX); On-site; USD 150,000 - 230,000; Full time

Job summary

Apple Inc. in Austin, TX seeks a seasoned SoC Physical Design Engineer to lead PD efforts for high-performance, low-power designs. You will drive RTL-to-GDSII implementation, PnR, STA, and sign-off, while guiding design rules and methodologies with cross-functional teams.

The role requires deep PD expertise, a track record of tapeouts, and the ability to meet tight schedules on large SOCs (>20M gates) at >1GHz. Join a collaborative, engineering-focused environment.

Qualifications

• BS degree required with 10+ years in physical design or related field.
• Experience with high-performance, low-power PD for large SOCs.
• Strong ability to lead cross-functional PD initiatives.

Responsibilities

• Own RTL2GDSII PD implementation from RTL to GDSII and PnR.
• Lead timing closure, STA, EMIR, and sign-off activities.
• Develop guidelines, checklists, and best-known methods for PD.

Skills

Floorplanning

Timing closure

Power optimization

Physical verification

PD architecture

RTL2GDS

Education

BS degree

Tools

Industry standard PD tools

Job description

Apple Inc. in Austin, TX seeks a seasoned SoC Physical Design Engineer to lead PD efforts for high-performance, low-power designs. You will drive RTL-to-GDSII implementation, PnR, STA, and sign-off, while guiding design rules and methodologies with cross-functional teams.

The role requires deep PD expertise, a track record of tapeouts, and the ability to meet tight schedules on large SOCs (>20M gates) at >1GHz. Join a collaborative, engineering-focused environment.