SoC Interconnect & Memory Systems ASIC Design Engineer

Anysilicon; San Diego (CA); On-site; USD 90,000 - 130,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an ASIC Design Engineer to work on SoC interconnect, cache, and memory systems. You will design RTL, validate subsystems, and collaborate with cross-functional teams to deliver high-performance silicon for mobile and automotive platforms.

The role emphasizes microarchitecture, hardware-feasibility reviews, and optimization across performance, power, and area. Strong RTL skills and programming proficiency are desired.

Qualifications

• Degree in EE/CE/CS or related field.
• 0–4 years in ASIC/SoC design or relevant academic experience.
• Exposure to RTL design and modern design flows.

Responsibilities

• Develop microarchitecture definitions for complex SoC subsystems.
• Design, implement, and validate RTL for interconnects, caches, memory subsystems.
• Collaborate with system architects to assess hardware feasibility.
• Optimize performance, power, area, timing, and scalability.
• Coordinate with verification to plan tests, review coverage, and debug.
• Support synthesis, timing closure, power analysis, and physical design.
• Participate in system-level integration and debugging across development.
• Investigate pre-silicon and post-silicon issues; contribute to C/C++ modeling.

Skills

Verilog/SystemVerilog RTL design

Computer Architecture

ASIC design methodologies

Digital logic design

C/C++/Python programming

Analytical problem solving

Communication & collaboration

Education

Bachelor's, Master's, or PhD in Electrical Engineering or Computer Engineering or Computer Science

Tools

Synopsys synthesis tools

Job description

Qualcomm Technologies, Inc. is seeking an ASIC Design Engineer to work on SoC interconnect, cache, and memory systems. You will design RTL, validate subsystems, and collaborate with cross-functional teams to deliver high-performance silicon for mobile and automotive platforms.

The role emphasizes microarchitecture, hardware-feasibility reviews, and optimization across performance, power, and area. Strong RTL skills and programming proficiency are desired.