Next-Gen System Cache RTL Design Engineer

Qualcomm; San Diego (CA); In loco; USD 122.000 - 183.000; Tempo pieno

Descrizione del lavoro

Qualcomm Technologies, Inc. in San Diego seeks an ASIC Engineer to define, model, design RTL for SOC interconnects and memory subsystems, and optimize power and performance. The role includes collaboration across teams to ensure high-quality IP for Snapdragon platforms.

You will verify and debug designs through full project cycles, work to reduce silicon cost, and contribute to low-power, high-performance solutions in a fast-paced, innovative environment.

Competenze

• Bachelor’s or higher in Science/Engineering; GPA>3.5 preferred.
• Experience with ASIC design, DV, integration or related work.
• PhD holders are eligible; multiple degrees welcome.

Mansioni

• Micro-architect, design and validate RTL for SOC interconnects and memory subsystems.
• Identify optimization opportunities for performance, power and cost.
• Verify and debug designs through full project cycles.
• Develop RTL from micro-architecture specifications.
• Support silicon bring-up and issue diagnosis.

Conoscenze

Verilog/SystemVerilog

Synopsys Synthesis

Low Power Design

Test Plan Development

Coverage-Based Verification

C/C++/Python

RTL Design for CPU/Cache

Communication

Formazione

Bachelor's degree GPA>3.5

Master's degree GPA>3.5

PhD in relevant field

Strumenti

RTL Design Tools

Descrizione del lavoro

Qualcomm Technologies, Inc. in San Diego seeks an ASIC Engineer to define, model, design RTL for SOC interconnects and memory subsystems, and optimize power and performance. The role includes collaboration across teams to ensure high-quality IP for Snapdragon platforms.

You will verify and debug designs through full project cycles, work to reduce silicon cost, and contribute to low-power, high-performance solutions in a fast-paced, innovative environment.