ASIC Design Engineer – SoC Interconnect, Cache & Memory Systems

Anysilicon; San Diego (CA); On-site; USD 90,000 - 130,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an ASIC Design Engineer to work on SoC interconnect, cache, and memory systems. You will design RTL, validate subsystems, and collaborate with cross-functional teams to deliver high-performance silicon for mobile and automotive platforms.

The role emphasizes microarchitecture, hardware-feasibility reviews, and optimization across performance, power, and area. Strong RTL skills and programming proficiency are desired.

Qualifications

• Degree in EE/CE/CS or related field.
• 0–4 years in ASIC/SoC design or relevant academic experience.
• Exposure to RTL design and modern design flows.

Responsibilities

• Develop microarchitecture definitions for complex SoC subsystems.
• Design, implement, and validate RTL for interconnects, caches, memory subsystems.
• Collaborate with system architects to assess hardware feasibility.
• Optimize performance, power, area, timing, and scalability.
• Coordinate with verification to plan tests, review coverage, and debug.
• Support synthesis, timing closure, power analysis, and physical design.
• Participate in system-level integration and debugging across development.
• Investigate pre-silicon and post-silicon issues; contribute to C/C++ modeling.

Skills

Verilog/SystemVerilog RTL design

Computer Architecture

ASIC design methodologies

Digital logic design

C/C++/Python programming

Analytical problem solving

Communication & collaboration

Education

Bachelor's, Master's, or PhD in Electrical Engineering or Computer Engineering or Computer Science

Tools

Synopsys synthesis tools

Job description

ASIC Design Engineer – SoC Interconnect, Cache & Memory Systems

Qualcomm Technologies, Inc. is seeking talented ASIC Design Engineers to join its Engineering Group, focusing on delivering industry-leading System-on-Chip (SoC) solutions. The role involves collaborating with various teams to develop high-performance, power-efficient silicon solutions for smartphones, PCs, automotive platforms, and emerging technologies.

Responsibilities:

• Develop microarchitecture definitions and design specifications for complex SoC subsystems.
• Design, implement, and validate RTL for SoC interconnects, cache controllers, memory subsystems, and DDR memory controller components.
• Collaborate with system architects to evaluate hardware feasibility of new features, algorithms, and performance requirements.
• Optimize designs for performance, power, area, timing, and scalability.
• Work closely with verification teams to develop test plans, review coverage, debug issues, and achieve design quality goals.
• Support synthesis, timing closure, power analysis, gate-level simulations, and physical design activities.
• Participate in system-level integration and debugging throughout the product development cycle.
• Investigate and resolve pre-silicon and post-silicon issues.
• Contribute to C/C++ modeling, design methodologies, and process improvements that enhance engineering productivity and design quality.
• Collaborate across cross-functional teams to successfully deliver silicon for production.

Qualifications:

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 0-4 years of industry experience or relevant academic experience in ASIC/SoC design.
• Experience or coursework in Verilog and/or SystemVerilog RTL design, Computer Architecture, ASIC design methodologies, Digital logic design, C, C++, and/or Python programming.
• Strong analytical and problem-solving skills.
• Excellent communication and collaboration skills.

Skills:

• SoC interconnects and on-chip communication fabrics
• Cache and memory subsystem design
• DDR/LPDDR memory controller architecture and design
• ARM or x86 processor architectures and bus protocols
• RTL development for CPUs, cache controllers, or memory controllers
• Functional verification and coverage-driven verification techniques
• Synopsys synthesis tools and ASIC implementation flows
• Timing closure, physical design support, and power optimization