Innovative System Cache ASIC Design Engineer

Anysilicon; San Diego (CA); Hybrid; USD 120,000 - 150,000; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego is seeking an ASIC Engineer to join the Engineering Group. The role focuses on high-performance, low-power SoC design and collaboration with cross-functional teams to drive innovation.

Responsibilities include RTL design and validation for interconnects, caches, and memory subsystems, optimizing performance and power while reducing silicon cost, and conducting verification across all project phases.

Qualifications

• Bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering or related field with GPA > 3.5.
• Master’s degree in the same fields with GPA > 3.5.
• PhD in a relevant field.

Responsibilities

• Micro-architect, design, and validate RTL for SoC interconnects, cache, and memory subsystems.
• Identify advanced optimization techniques for performance and power efficiency.
• Evaluate hardware feasibility for complex algorithms and requirements.
• Create RTL corresponding to the developed microarchitecture.
• Conduct verification and debugging throughout project cycles.
• Optimize silicon cost and improve clock speed.
• Troubleshoot silicon issues related to the design.

Skills

Verilog/SystemVerilog

Synopsys synthesis

Low power design

C/C++/Python

RTL design

Collaboration

Education

Bachelor's degree with GPA > 3.5

Master's degree GPA > 3.5

PhD in a relevant field

Job description

Qualcomm Technologies, Inc. in San Diego is seeking an ASIC Engineer to join the Engineering Group. The role focuses on high-performance, low-power SoC design and collaboration with cross-functional teams to drive innovation.

Responsibilities include RTL design and validation for interconnects, caches, and memory subsystems, optimizing performance and power while reducing silicon cost, and conducting verification across all project phases.