Next-Gen Cache & SoC RTL Design Engineer

QUALCOMM, Inc.; San Diego (CA); On-site; USD 122,000 - 183,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an ASIC Engineer to define, model, and design RTL for SOC Interconnects, caches, and memory subsystems, with a focus on high performance and low power.

You will verify, validate, implement, and document IP development for Qualcomm Snapdragon platforms across smartphones, PCs, VR/AR, and automotive solutions. The team seeks candidates with Verilog/SystemVerilog, Synopsys synthesis, low power design, and DV experience; programming in C/C++/Python is a plus.

Qualifications

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with a GPA above 3.5; Master’s or PhD preferred.
• Experience or coursework in Verilog/SystemVerilog design and DV methodologies.
• Familiarity with computer architecture, low-power design, and programming languages (C/C++/Python).

Responsibilities

• Micro-architect, design and validate RTL for blocks and modules of SOC Interconnects, Interconnect Caches and memory subsystems.
• Identify advanced ways to optimize hardware design for better performance, power, and cost.
• Evaluate hardware feasibilities of complex algorithms and requirements.
• Develop micro-architecture and specification of the new generation design.
• Develop RTL for the corresponding micro-architecture.
• Provide essential verification and debugging activities throughout the project cycles.
• Optimize silicon cost and improve clock speed.
• Troubleshoot silicon issues with products relevant to the design.

Skills

Verilog/SystemVerilog

C/C++/Python

Low power design

Test plan development

Design verification

Education

Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with GPA > 3.5

Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with GPA > 3.5

PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field

Tools

Synopsys Synthesis

RTL tooling

Job description

Qualcomm Technologies, Inc. is seeking an ASIC Engineer to define, model, and design RTL for SOC Interconnects, caches, and memory subsystems, with a focus on high performance and low power.

You will verify, validate, implement, and document IP development for Qualcomm Snapdragon platforms across smartphones, PCs, VR/AR, and automotive solutions. The team seeks candidates with Verilog/SystemVerilog, Synopsys synthesis, low power design, and DV experience; programming in C/C++/Python is a plus.