Principal Engineer, SoC Design

Kepler Computing; San Jose (CA); On-site; USD 250,000 - 310,000; Full time

Job summary

Kepler Computing is seeking a seasoned SoC Chip Lead to own chip implementation from architecture to tapeout and post-silicon validation. You will drive front-end design, verification integration, and physical design coordination with DFT/DFX, packaging, and manufacturing interactions.

Lead a team across architecture, verification, and manufacturing, setting best practices and sign-off processes while mentoring engineers through planning and risk mitigation in a fast-paced environment.

Qualifications

• 15+ years of hands-on SoC front-end design and tapeouts.
• Deep expertise in on-chip interconnect and IO subsystems.
• Strong knowledge of floorplanning, timing convergence, power integrity.
• Experience with lint, CDC/RDC, LEC, synthesis, SDC, and formal verification.
• Solid DFT/DFX methods: ATPG, MBIST and JTAG.
• Proficiency with Python, Perl, Tcl, Shell.
• Excellent leadership and communication skills.

Responsibilities

• Own chip implementation end to end: front-end design, verification integration, physical design coordination, DFT/DFX, packaging and manufacturing interaction.
• Drive design-to-spec execution: lint, CDC, LEC, synthesis, SDC constraints and full design convergence.
• Evaluate and integrate IP, weighing trade-offs across performance, power, area, cost and schedule.
• Work with architecture, verification, DFX, physical design, packaging and manufacturing teams so implementation decisions are physically feasible and on schedule.
• Set and enforce implementation best practices, review standards and sign-off infrastructure.
• Lead and mentor design and implementation engineers. Drive planning, resourcing and risk mitigation.

Skills

SoC design

Tapeouts

Interconnect design

Power management

Physical design

DFT/DFX

EDA tools

Scripting: Python

Education

EE/CE degree

Tools

EDA tools

Job description

About The Role

We’re looking for a highly experienced SoC Chip Lead to own chip implementation for Kepler's products. In this high-impact technical leadership role, you'll lead the design, verification and physical design teams from micro-architecture through tapeout and post-silicon validation.

Responsibilities

• Own chip implementation end to end: front-end design, verification integration, physical design coordination, DFT/DFX, packaging and manufacturing interaction.
• Drive design-to-spec execution: lint, CDC, LEC, synthesis, SDC constraints and full design convergence.
• Evaluate and integrate IP, weighing trade-offs across performance, power, area, cost and schedule.
• Work with architecture, verification, DFX, physical design, packaging and manufacturing teams so implementation decisions are physically feasible and on schedule.
• Set and enforce implementation best practices, review standards and sign-off infrastructure.
• Lead and mentor design and implementation engineers. Drive planning, resourcing and risk mitigation.

Requirements

• B.Tech/M.Tech/MS in EE, ECE, Computer Engineering or a related field.
• 15+ years of hands-on SoC front-end design and implementation experience, with multiple successful high-performance tapeouts.
• Deep expertise in on-chip interconnect, power management and IO subsystem design.
• Strong working knowledge of physical design: floorplanning, timing convergence and power integrity.
• Hands-on experience with lint, CDC/RDC, LEC, synthesis, SDC development and formal verification.
• Solid knowledge of DFT/DFX methods: scan insertion, ATPG, MBIST and JTAG.
• Skilled with industry-standard EDA tools across the implementation stack.
• Strong scripting skills (Python, Perl, Tcl, Shell).
• Excellent leadership and communication skills with a proven ability to drive complex programs in a fast-paced environment.

Nice to Have

• Experience with 3D innovations
• Background in high-bandwidth memory subsystem design.
• Familiarity with AI workloads and their memory demands.
• Experience with emulation and prototyping platforms.
• Prior startup experience delivering silicon with lean teams and aggressive schedules.

Compensation And Benefits

Actual compensation will be determined based on factors including, but not limited to, relevant experience, skills, qualifications, education, job responsibilities and work location.

Kepler offers a comprehensive benefits package to eligible employees, including medical, dental and vision coverage, retirement benefits, time off and additional Kepler benefits as applicable. Eligibility and benefit offerings may vary based on employment status and work location.

Compensation Range: $250K - $310K

Equal Employment Opportunity

Kepler is an Equal Opportunity Employer. We provide equal employment opportunities to all applicants and employees and do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, or any other characteristic protected under applicable federal, state, or local law.

We believe that different backgrounds, experiences, perspectives and ideas make our team stronger and help our employees, our technology and our community thrive.

Reasonable Accommodation

Kepler is committed to providing reasonable accommodations to qualified individuals with disabilities throughout the application and hiring process. If you need a reasonable accommodation to participate in the application or interview process, please contact us at 408-365-4627 or [e-mail].

Fair Chance Hiring

Kepler will consider qualified applicants with criminal histories in accordance with applicable federal, state, and local laws, including the California Fair Chance Act. Applicants are not required to disclose criminal history before a conditional offer of employment except where otherwise permitted or required by applicable law.

Federal Contractor Notice

Kepler is a federal contractor or subcontractor and is committed to its obligations regarding equal employment opportunity. Kepler does not discriminate against qualified individuals on the basis of disability or protected veteran status and takes steps to employ and advance in employment qualified individuals with disabilities and protected veterans.