SoC Front-End Lead & RTL Architect

TylSemi; San Jose (CA); Remote; USD 200,000 - 260,000; Full time

Job summary

TYLsemi, Inc. seeks a SoC Front-End Lead to drive technical direction, micro-architecture, and logic design of next-generation chips.

You will guide front-end execution from micro-architecture to netlist delivery and lead a team of hardware design engineers across emulation and firmware collaborations. You will define design methodologies, partition blocks, own data flow and interfaces, oversee IP/SoC integration (PCIe/UCIe/CXL), and apply AI-assisted flows to accelerate RTL generation and

Qualifications

• 12+ years of digital design and RTL development experience.
• Expert proficiency in SystemVerilog/Verilog for high-performance SoCs.
• Hands-on with front-end tools for Lint, CDC, and formal checks.

Responsibilities

• Lead front-end design team; set design methodologies and timelines.
• Translate product requirements into micro-architectural specs and partition blocks.
• Oversee IP/SoC integration (PCIe/UCIe/CXL) and power/clock management.
• Drive AI-assisted design automation to accelerate RTL work.
• Ensure front-end signoff quality with CDC/RDC/LEC checks.
• Collaborate with physical design and DV/DFT teams; support silicon bring-up.

Skills

RTL design

SystemVerilog

Code reviews

Front-end tools

Clock domain

Power management

Cross-functional

Verilog

IP/SoC integration

Education

Bachelor's or Master's in EE/CE

Tools

SpyGlass

VC Formal

JasperGold

Job description

TYLsemi, Inc. seeks a SoC Front-End Lead to drive technical direction, micro-architecture, and logic design of next-generation chips.

You will guide front-end execution from micro-architecture to netlist delivery and lead a team of hardware design engineers across emulation and firmware collaborations. You will define design methodologies, partition blocks, own data flow and interfaces, oversee IP/SoC integration (PCIe/UCIe/CXL), and apply AI-assisted flows to accelerate RTL generation and