Lead SoC Verification Architect — AI-Driven DV

TylSemi; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Stock options

Remote-friendly team

Job summary

TYLsemi seeks a seasoned SoC Design Verification Lead to architect and drive verification strategy for next-generation semiconductor products. You will lead a team of verification engineers, defining testbenches, regressions, and automation to ensure first-time-right silicon.

You will collaborate with Front-End, Emulation, and Firmware teams, applying formal methods, SVA, AI-driven techniques, and advanced DV to validate complex blocks, subsystems, and full-chip fabrics.

Qualifications

• 12+ years of hardware verification experience with tape-out success on complex SoCs.
• Master-level proficiency in SystemVerilog and UVM.
• Deep expertise in constrained-random verification, functional coverage, and SVA.
• Experience with major EDA simulators and debug platforms.
• Strong analytical and cross-functional communication skills.

Responsibilities

• Lead, mentor, and grow the verification team; architect the verification environment.
• Translate architectures into comprehensive verification plans and stress test edge cases.
• Own environment architecture using SystemVerilog and UVM; deploy AI-driven methods.
• Apply formal verification, SVA, and HW/SW co-verification where beneficial.
• Oversee IP and SoC verification, including power, clocking, and security features.
• Track coverage and sign-off criteria; coordinate with Front-End and Post-Silicon teams.

Skills

SystemVerilog

UVM

Constrained-random verif.

Formal verification

SVA

Leadership

Education

Bachelor’s or Master’s in Electrical/Computer Engineering, CS

Tools

Cadence

Synopsys

Mentor Graphics

Emulation platforms

Job description

TYLsemi seeks a seasoned SoC Design Verification Lead to architect and drive verification strategy for next-generation semiconductor products. You will lead a team of verification engineers, defining testbenches, regressions, and automation to ensure first-time-right silicon.

You will collaborate with Front-End, Emulation, and Firmware teams, applying formal methods, SVA, AI-driven techniques, and advanced DV to validate complex blocks, subsystems, and full-chip fabrics.