Senior SoC Architect for Chiplet Interconnect & IO

TylSemi, Inc.; San Jose (CA); On-site; USD 175,000 - 350,000; Full time

Job summary

TylSemi, Inc. in San Jose, California, is seeking a SoC Architect to define and drive the architecture of next-generation infrastructure.

This role owns system and SoC architecture from concept to silicon, with emphasis on scalability, performance, interconnects, and system-level optimization. You will lead system architecture for complex SoCs, drive modular chiplet-based designs (UCIe), optimize data movement across PCIe/UCIe/CXL, and collaborate with design and DV teams to ensure feasibility

Qualifications

• 18+ years in SoC or system architecture.
• Proven track record architecting complex SoCs for AI/HPC.
• Deep understanding of system-level design, IO, and interconnects.
• Experience with performance modeling and architectural simulation.

Responsibilities

• Define system architecture for complex SoCs, including IO, compute, interconnects.
• Drive scalable, modular chiplet-based designs (UCIe) and architecture direction.
• Architect high-performance data movement across IO interfaces (PCIe/UCIe/CXL).
• Collaborate with design and DV teams to ensure feasibility and efficient implementation.
• Develop performance models and simulations to validate choices.
• Set system-level verification strategies and long-term roadmap.

Skills

SoC architecture

System architecture

Performance modeling

Hardware design

Cross-functional collaboration

High-speed IO

Education

Bachelor’s/Master’s/PhD in Electrical Engineering or Computer Engineering

Tools

UCIe

PCIe

CXL

HBM/D RAM

Job description

TylSemi, Inc. in San Jose, California, is seeking a SoC Architect to define and drive the architecture of next-generation infrastructure.

This role owns system and SoC architecture from concept to silicon, with emphasis on scalability, performance, interconnects, and system-level optimization. You will lead system architecture for complex SoCs, drive modular chiplet-based designs (UCIe), optimize data movement across PCIe/UCIe/CXL, and collaborate with design and DV teams to ensure feasibility