SoC Front-End Lead — AI-Scale Silicon, Remote-Friendly

TylSemi, Inc.

San Jose (CA)

On-site

USD 210,000 - 270,000

Full time

5 days ago
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Job summary

TylSemi, Inc. in San Jose, CA, is seeking a SoC Front-End Lead to guide the technical direction from micro-architecture to netlist delivery. You will manage a team of hardware design engineers and partner with Emulation and Firmware to deliver high-performance, low-power silicon.

You will translate requirements into architecture, oversee IP/SoC integration, and accelerate design velocity with AI-powered tools while ensuring signoff readiness with static verification and CDC checks.

Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering or related field.
  • 12+ years of digital design and RTL development experience.
  • Expert in SystemVerilog/Verilog for high-performance design.
  • Hands-on experience with front-end tools for linting, CDC, and formal checks.
  • Strong understanding of clock/reset and power intent (UPF/CPF).

Responsibilities

  • Lead and scale the frontend design team; set methodology and timelines.
  • Translate product requirements into micro-architectures and block interfaces.
  • Oversee IP/SoC integration and interfaces (PCIe, UCIe, CXL).
  • Drive AI-assisted design automation and RTL review workflows.
  • Collaborate with physical design to address timing and area early.
  • Work with DV/DFT teams to define tests and debug RTL.

Skills

RTL design
SystemVerilog
EDA tools
Cross-functional leadership

Education

Bachelor’s in Electrical Engineering
Master’s in Electrical Engineering

Tools

Synopsys SpyGlass
VC Formal
Cadence JasperGold

Job description

TylSemi, Inc. in San Jose, CA, is seeking a SoC Front-End Lead to guide the technical direction from micro-architecture to netlist delivery. You will manage a team of hardware design engineers and partner with Emulation and Firmware to deliver high-performance, low-power silicon.

You will translate requirements into architecture, oversee IP/SoC integration, and accelerate design velocity with AI-powered tools while ensuring signoff readiness with static verification and CDC checks.

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