Senior Debug Verification Engineer — SoC/FPGA & UVM Expert

SwiftCruit; San Jose (CA); On-site; USD 149,100 - 215,000; Full time

Job summary

SwiftCruit in San Jose, California is seeking a Sr. Debug Design Verification Engineer. This role focuses on design for debug architecture verification tasks, requiring strong expertise in complex ASIC designs and UVM methodology. The successful candidate will create test cases, work with cross-functional teams, and ensure full coverage verification plans.

The position offers a salary range of $149,100 - $215,000 USD and requires a minimum of 8 years of experience in relevant fields.

Qualifications

• Minimum 8+ years of experience with complex ASIC designs and/or verification.
• Minimum 8+ years of experience with SystemVerilog language.
• Minimum 8+ years of experience on UVM verification methodology.
• Minimum 8+ years of experience scripting in Linux/Unix environments.
• Strong communication skills and ability to work in a team.

Responsibilities

• Conduct pre-silicon system verification for SoC and FPGA designs.
• Create test cases and testbenches using UVM methodology.
• Experience with Design for Debug architecture verification.
• Coordinate with Design, SW, and Architecture teams for verification plans.

Skills

Complex ASIC designs

SystemVerilog language

UVM verification methodology

Scripting in Linux/Unix

Communication skills

Job description

SwiftCruit in San Jose, California is seeking a Sr. Debug Design Verification Engineer. This role focuses on design for debug architecture verification tasks, requiring strong expertise in complex ASIC designs and UVM methodology. The successful candidate will create test cases, work with cross-functional teams, and ensure full coverage verification plans.

The position offers a salary range of $149,100 - $215,000 USD and requires a minimum of 8 years of experience in relevant fields.