SoC/ASIC Design Engineer — RTL & FPGA Config

AMD; San Jose (CA); On-site; USD 90,000 - 130,000; Full time

Benefits offered by this job

Comprehensive benefits package

Job summary

A leading technology company located in San Jose is seeking motivated candidates for a role involving complex microarchitectural design and FPGA configuration. The ideal applicant has a Bachelor’s or Master’s in Electrical or Computer Engineering, and a background in ASIC design with skills in Verilog, System Verilog, and collaboration across multiple teams. This role is pivotal for driving next-generation configuration solutions and requires strong communication and analytical skills.

Qualifications

• Proven background experiences in ASIC design.
• Knowledge of on‑chip interconnect protocols (AMBA AXI/AXI‑S/APB).
• Experience in designs with multiple power domains and UPF.

Responsibilities

• Author microarchitecture specification and own RTL implementation.
• Collaborate with hardware, firmware, and software teams.
• Drive design from specifications through production.

Skills

Strong communication skills

Analytical skills

Problem-solving skills

Collaboration across domains

Education

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

Tools

Verilog

System Verilog

ASIC CAD tools

SDC timing constraints

Scripting languages (Perl, Python)

Job description

A leading technology company located in San Jose is seeking motivated candidates for a role involving complex microarchitectural design and FPGA configuration. The ideal applicant has a Bachelor’s or Master’s in Electrical or Computer Engineering, and a background in ASIC design with skills in Verilog, System Verilog, and collaboration across multiple teams. This role is pivotal for driving next-generation configuration solutions and requires strong communication and analytical skills.