Senior ASIC/VLSI Design Engineer - RTL, DFT & Bring-up

Retym Israel Ltd; Cupertino (CA); On-site; USD 100,000 - 130,000; Full time

Job summary

A tech company in Cupertino is seeking an experienced ASIC/VLSI Design Engineer to design innovative communication systems. The role involves collaboration with multiple teams, RTL coding, and optimization of design for performance. Candidates should have over 5 years in digital design with strong Verilog/System-Verilog skills and educational background in electrical or computer engineering. This position allows creativity and independence in a cutting-edge environment.

Qualifications

• +5 years of experience as ASIC/VLSI digital design engineer.
• Strong team player with solid interpersonal skills.
• Ability to work independently and self-motivated.

Responsibilities

• Work closely with Algorithm and Architecture teams.
• Interpret protocol specifications and apply them in design.
• Participate in micro-architecture definition and RTL coding.
• Collaborate with verification, DFT, and backend teams.
• Optimize for Area, Power, and Performance (PPA).

Skills

Verilog/System-Verilog experience

Simulation tools/environments

Verification methodologies

Team player

Entrepreneurial attitude

Education

BS/MS in EE/CE from leading universities

Tools

Python

Perl

TCL

Job description

A tech company in Cupertino is seeking an experienced ASIC/VLSI Design Engineer to design innovative communication systems. The role involves collaboration with multiple teams, RTL coding, and optimization of design for performance. Candidates should have over 5 years in digital design with strong Verilog/System-Verilog skills and educational background in electrical or computer engineering. This position allows creativity and independence in a cutting-edge environment.