ASIC Design Engineer - FPGA/RTL & Tapeout Readiness

Jobsbridge; San Jose (CA); On-site; USD 100,000 - 130,000; Full time

Job summary

A staffing solutions company is searching for an ASIC Engineer with 2-5 years of experience in FPGA/ASIC development to work on digital circuit designs in San Jose, CA. The role involves building RTL designs, collaborating with internal teams, and writing verification test cases. Candidates should have skills in ASIC design and tools like Cadence. This is a fast-paced environment focused on achieving successful outcomes in ASIC development.

Qualifications

• 2-5 years of experience in FPGA/ASIC Development.
• Build RTL designs of digital circuits using VHDL and System Verilog.
• Collaborate with architecture and verification teams.

Responsibilities

• Perform frontend design development and integration of large ASIC designs.
• Write design documents including high-level interface descriptions.
• Write function test cases to verify functionality of designs.

Skills

ASIC Design

FPGA

RTL Design

Chip Architecture

Implementation

Synthesis /Conformal (Cadence Tool)

Job description

A staffing solutions company is searching for an ASIC Engineer with 2-5 years of experience in FPGA/ASIC development to work on digital circuit designs in San Jose, CA. The role involves building RTL designs, collaborating with internal teams, and writing verification test cases. Candidates should have skills in ASIC design and tools like Cadence. This is a fast-paced environment focused on achieving successful outcomes in ASIC development.