Silicon Packaging Design Engineer: Substrate Innovator

Intel Corporation; Phoenix (AZ); On-site; USD 106,000 - 149,000; Full time

Job summary

Intel is seeking a Silicon Packaging Design Engineer in Phoenix to drive end-to-end substrate design from concept to tape-out, ensuring performance, cost efficiency, and manufacturability. You will work with silicon and hardware teams to deliver cutting-edge, high-performance solutions.

The role involves layout, routing, design rule development, and cross-functional collaboration to optimize pinout and silicon-package-board interactions. On-site presence is required in Arizona.

Qualifications

• Bachelor's with 1+ years of experience or master's with 6 months of experience in Electrical Engineering, Mechanical Engineering, or Materials disciplines.
• 6+ months of experience with microelectronic package or PCB physical layout design and manufacturing process.
• Familiarity with package design tools like Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks.

Responsibilities

• Drive the physical layout and routing of package designs, ensuring alignment with silicon, package, and board performance requirements.
• Perform substrate fit and routing studies to establish design, performance, and cost tradeoffs.
• Define and implement substrate design rules, conducting internal and external reviews to ensure designs meet quality standards.
• Analyze data, resolve DRCs, and optimize package designs for manufacturability and performance.
• Collaborate with cross-functional teams to optimize pinout and silicon-package-board interactions.
• Complete documentation and collateral into the product lifecycle management system of record.

Skills

Electrical Engineering

Mechanical Engineering

Materials Science

Microelectronic package layout

PCB layout familiarity

Education

Bachelor's degree in Electrical Engineering

Bachelor's degree in Mechanical Engineering

Bachelor's degree in Materials Science

Tools

Siemens Xpedition

Cadence Allegro Package Design

AutoCAD

SolidWorks

Job description

Intel is seeking a Silicon Packaging Design Engineer in Phoenix to drive end-to-end substrate design from concept to tape-out, ensuring performance, cost efficiency, and manufacturability. You will work with silicon and hardware teams to deliver cutting-edge, high-performance solutions.

The role involves layout, routing, design rule development, and cross-functional collaboration to optimize pinout and silicon-package-board interactions. On-site presence is required in Arizona.