Silicon Packaging Design Engineer

Intel Corporation; Phoenix (AZ); On-site; USD 106,000 - 149,000; Full time

Job summary

Intel is seeking a Silicon Packaging Design Engineer in Phoenix to drive end-to-end substrate design from concept to tape-out, ensuring performance, cost efficiency, and manufacturability. You will work with silicon and hardware teams to deliver cutting-edge, high-performance solutions.

The role involves layout, routing, design rule development, and cross-functional collaboration to optimize pinout and silicon-package-board interactions. On-site presence is required in Arizona.

Qualifications

• Bachelor's with 1+ years of experience or master's with 6 months of experience in Electrical Engineering, Mechanical Engineering, or Materials disciplines.
• 6+ months of experience with microelectronic package or PCB physical layout design and manufacturing process.
• Familiarity with package design tools like Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks.

Responsibilities

• Drive the physical layout and routing of package designs, ensuring alignment with silicon, package, and board performance requirements.
• Perform substrate fit and routing studies to establish design, performance, and cost tradeoffs.
• Define and implement substrate design rules, conducting internal and external reviews to ensure designs meet quality standards.
• Analyze data, resolve DRCs, and optimize package designs for manufacturability and performance.
• Collaborate with cross-functional teams to optimize pinout and silicon-package-board interactions.
• Complete documentation and collateral into the product lifecycle management system of record.

Skills

Electrical Engineering

Mechanical Engineering

Materials Science

Microelectronic package layout

PCB layout familiarity

Education

Bachelor's degree in Electrical Engineering

Bachelor's degree in Mechanical Engineering

Bachelor's degree in Materials Science

Tools

Siemens Xpedition

Cadence Allegro Package Design

AutoCAD

SolidWorks

Job description

Job Details: Job Description: As a Silicon Packaging Design Engineer, you will play a pivotal role in driving the development of advanced substrate designs, contributing to the creation of cutting‑edge technology that fuels Intel's innovation. You will be responsible for the end‑to‑end development of substrate designs, from concept through tape‑out, ensuring optimal performance, cost efficiency, and manufacturability. This position provides an exciting opportunity to work collaboratively with silicon and hardware teams, directly impacting Intel's success in delivering world‑class solutions for high‑performance applications.

Key Responsibilities

• Drive the physical layout and routing of package designs, ensuring alignment with silicon, package, and board performance requirements.
• Perform substrate fit and routing studies to establish design, performance, and cost tradeoffs.
• Define and implement substrate design rules, conducting internal and external reviews to ensure designs meet quality standards.
• Analyze data, resolve Design Rule Checks (DRCs), and optimize package designs for manufacturability and performance.
• Collaborate with cross‑functional teams to optimize pinout and silicon‑package‑board interactions.
• Complete documentation and collateral into the product lifecycle management system of record.

Behavioral traits

• Problem‑solving skills and a proactive approach to challenges.
• Excellent communication and interpersonal skills for effective cross‑functional collaboration.
• Manage multiple tasks and projects simultaneously under tight deadlines.

Qualifications

Minimum Qualifications

• Minimum Qualifications Bachelors with 1+ years of experience or master’s degree with 6 months of experience in Electrical Engineering, Mechanical Engineering, or Material Sciences disciplines.
• 6+ months of experience with the following technical skills: Experience and/or familiarity with microelectronic package or PCB physical layout design and manufacturing process. Familiarity with package design tools like Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks. Familiarity with physical layout aspects of substrate design, including custom layouts, floor plans, or schematic layout conversion.

Preferred Qualifications

• Experience in microelectronic package substrate design, package I/O routing, and/or technology development.
• Familiarity with microelectronic package electrical modeling and simulation tools such as PowerDC, HyperLynx, Q3D, and HFSS.
• Experience with package design tools such as Package Layout Automation (PLA) and FIELD.
• Experience with scripting using Python, VB, C, or similar languages.

Job Type: College Grad Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations:

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role This role will require an on‑site presence.

* Job posting details (such as work model, location or time type) are subject to change.

* ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website.