Senior Silicon Packaging & PCB Integration Engineer

Intel; Phoenix (AZ); On-site; USD 164,470 - 232,190; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel in United States, Arizona, Phoenix is seeking an experienced Silicon Packaging Design Engineer to drive end-to-end test board development, from concept through tapeout. You will lead planning, routing studies, and layout while ensuring manufacturability, performance, and cost targets.

The role requires deep PCB design expertise, signal integrity focus, and close collaboration with package design, test engineering, and validation teams to optimize package-board interactions and system

Qualifications

• Master's degree in Electrical Engineering or Mechanical Engineering.
• +10 years of PCB layout experience using Cadence Allegro and Cadence Constraint Manager.
• +5 years in hardware development including Schematic Entry, Signal Integrity, and Power Delivery, with constraint entry, library creation, DFM/DFX.
• Experience managing highly complex PCB designs across multiple sites.
• Expertise in board design, interconnect methodologies, and manufacturability principles.
• Expertise in various board technologies and manufacturing processes.
• Proven ability to resolve board design rules and DR C violations.
• Preferred: experience with Siemens Xpedition.
• 8+ years with HDI/Type4 PCB technology.
• Experience communicating with board manufacturers to obtain design approvals.
• Experience aligning internal design rules with vendor capabilities.
• Experience managing external CAD contract workers.
• Ability to manage multiple projects and cross-disciplinary teams in a fast-paced environment.

Responsibilities

• Drive end-to-end development of test board designs from concept through tapeout.
• Perform board planning, floor planning, routing studies, and physical layout implementation.
• Conduct board fit and routing studies to evaluate design, performance, manufacturability, and cost tradeoffs.
• Partner closely with package design, test engineering, and validation teams to define board requirements and optimize package-board interactions.
• Develop and validate board connectivity, ensuring design integrity and compliance with project specifications.
• Perform design rule checks (DRCs) and manufacturing design rule validation to ensure successful fabrication and assembly.
• Lead internal and external design reviews and drive resolution of design issues and DRC violations.
• Collaborate with board fabrication and assembly vendors to obtain design approval and support manufacturing readiness.
• Define and maintain board design guidelines, standards, and best practices.
• Analyze design data and technical results to identify opportunities for optimization and continuous improvement.
• Create and maintain design documentation and release collateral within PLM systems.
• Support root cause analysis and troubleshooting activities related to board design, package-board integration, and test hardware performance.

Skills

Cadence Allegro

Cadence Constraint Manager

Schematic Entry

Signal Integrity

Power Delivery

DFM

DFX

Board design

Interconnect methodologies

Education

Master's degree in Electrical Engineering or Mechanical Engineering

Tools

Siemens Xpedition

Job description

Intel in United States, Arizona, Phoenix is seeking an experienced Silicon Packaging Design Engineer to drive end-to-end test board development, from concept through tapeout. You will lead planning, routing studies, and layout while ensuring manufacturability, performance, and cost targets.

The role requires deep PCB design expertise, signal integrity focus, and close collaboration with package design, test engineering, and validation teams to optimize package-board interactions and system