Silicon Manufacturing Test Engineer - Equity Eligible

Salesonaut; Santa Clara (CA); Hybrid; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA’s Silicon Co-Design Group in Santa Clara is seeking a skilled engineer to lead and optimize silicon post-silicon validation and high-volume testing. You will develop closed-loop analysis for VF characteristics, support PVT spec validation across manufacturing, and partner with multiple HW teams to shape test coverage for scalable screen setups.

Qualifications include 3+ years of relevant post-silicon validation, hands-on lab bring-up, strong EE fundamentals, and proficiency in Python,

Qualifications

• Bachelor's or Master's degree in Microelectronics/Electrical/Electronic/Computer Engineering or equivalent.
• 3+ years of silicon PVT validation or high-volume manufacturing testing experience.
• Hands-on lab experience with silicon bring-up, lab debug, shmoo analysis, VF characteristics, test content bring-up, and correlation to Si characterization, yield, and coverage optimization.

Responsibilities

• Develop and implement robust closed-loop analysis for VF characteristics and POR expectations for MFG screening diagnostics.
• Support VF/VMIN/VMAX/PVT spec validation and productization across Manufacturing teams.
• Collaborate with HW engineering teams to determine test coverage and constraints for high-volume manufacturing screens.
• Assist prototyping and fine-tune speed, power, circuits, yield, and silicon coverage in SLT socketed environment.
• Coordinate SLT/BLT testing flows and translate learnings into shift-left improvements.
• Drive process improvements through root cause analysis and data analytics.

Skills

Data analysis

Lab debugging

Problem solving

Python

Education

Bachelor's or Master's degree in Microelectronics/Electrical/Electronic/Computer Engineering

Tools

BASH

Linux

Scripting

Job description

NVIDIA’s Silicon Co-Design Group in Santa Clara is seeking a skilled engineer to lead and optimize silicon post-silicon validation and high-volume testing. You will develop closed-loop analysis for VF characteristics, support PVT spec validation across manufacturing, and partner with multiple HW teams to shape test coverage for scalable screen setups.

Qualifications include 3+ years of relevant post-silicon validation, hands-on lab bring-up, strong EE fundamentals, and proficiency in Python,