Senior Silicon Product Engineer - Manufacturing

NVIDIA Corporation; Santa Clara (CA); Hybride; USD 168 000 - 265 000; Plein temps

Résumé du poste

NVIDIA in Santa Clara is seeking a seasoned silicon validation engineer to drive post-silicon PVT validation and SLT testing for GPUs/SoCs. You will collaborate with hardware and software teams, refine test coverage, and optimize data-driven diagnostics to improve silicon yield and coverage in a high-volume screening environment.

Requires 8+ years in post-silicon validation, strong lab skills, Python/BASH/Linux, and proven cross-functional leadership.

Qualifications

• 8+ years of silicon Post-silicon PVT validation or HVM testing experience.
• Hands-on lab experience with silicon bring-up and test content bring-up.
• Strong data analysis and cross-functional alignment skills.

Responsabilités

• Collaborate with HW/SW teams to define test coverage and SLT test flows.
• Co-design SLT testability scope and coverage enhancements for high-volume manufacturing screens.
• Develop and maintain SLT testing flows and correlate to Si characterization and yield.

Connaissances

Post-silicon validation

Python

BASH

Linux

Data analysis

Formation

Bachelor’s or Master’s in Microelectronics/Electrical/Electronic/Computer Engineering

Outils

Lab testing tools

Description du poste

What you will be doing:

Partner multi-functionally with HW engineering teams such as Silicon PVT design and characterization teams, IO design and validation teams, system feature owners, SLT and BLT Production Operations, etc., to determine test coverage and constraints to resolve appropriate SLT test conditions, test content, and flows for high-volume manufacturing screens. Partner with SW and platform teams to support and improve SLT testing infrastructure, debug knobs, and data collection features needed to support manufacturing screens effectively. Co-design SLT testability scope and coverage enhancements for Nvidia's manufacturing testing with a focus on high-volume system-level manufacturing screens. Prototype and fine-tune speed, power, circuits, yield, and quality for effective silicon coverage in the SLT socketed environment. Co-design, develop, and maintain SLT testing flows and incorporate takeaways from silicon and correlate to design. Define procedures to facilitate Silicon correlation activities between production testing infrastructure and internal Si characterization and diagnostics programs. Support customer-facing and quality teams during customer escalations to understand the issues and fix gaps identified in SLT production coverage. Drive alignment for manufacturability, test time optimization and reduction, cost vs. coverage tradeoffs, etc., to evaluate the effectiveness of new tests. Initiate and drive process improvements and preventative actions through root cause analysis and data analytics.

What we need to see:

Bachelor’s or Master’s Degree or equivalent in Microelectronics/Electrical/Electronic/Computer Engineering or equivalent experience. 8+ years of relevant proven experience in silicon Post-silicon PVT validation and/or High-volume manufacturing testing for sophisticated SoCs, GPUs, CPUs, or similar. Hands-on lab experience with silicon bring-up, lab debug, test content bring-up, and correlation to Si characterization, yield, and coverage optimization. Strong EE fundamentals, device physics, knowledgeable in Silicon design, statistics, STA concepts, signal integrity, fault analysis, sampling, and computer architecture. Excellent interpersonal skills and demonstrated ability to drive multi-functional alignment around plans, dependencies, and sign-off criteria. Prior ownership of manufacturing test strategy for a major silicon product (e.g., GPU/SoC/CPU) from early planning through ramp to QS/production. Strong data analysis skills. Prior experience working with volume data is a plus. Good understanding of firmware/driver structures and their interaction with HW. Problem-solving, debugging, analysis, and logical reasoning skills with examples to prove it. Experience with Python, BASH, Linux, and scripting.

Ways to stand out above the crowd:

Outstanding work ethic and up-leveling discussions to solve the real problems Native use of AI tools to accelerate production testing and debug workflows Battle-tested on GPUs, CPUs, AI accelerators, or other large-scale SoCs — you’ve seen firsthand how complexity at scale reshapes the failure landscape and demands a different level of engineering intuition. Co-designed or led multi-functional alignment on production methodologies adopted by other teams in a High Volume Manufacturing(HVM) environment. #LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 20, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer.

As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA pioneered accelerated computing. Today, our AI infrastructure powers global intelligence, transforming every industry.

Learn more about NVIDIA.