Silicon Product Engineer - Manufacturing

Nvidia Corporation; Santa Clara (CA); Hybrid; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA’s Silicon Co-Design Group in Santa Clara is seeking a skilled engineer to lead and optimize silicon post-silicon validation and high-volume testing. You will develop closed-loop analysis for VF characteristics, support PVT spec validation across manufacturing, and partner with multiple HW teams to shape test coverage for scalable screen setups.

Qualifications include 3+ years of relevant post-silicon validation, hands-on lab bring-up, strong EE fundamentals, and proficiency in Python,

Qualifications

• Bachelor's or Master's degree in Microelectronics/Electrical/Electronic/Computer Engineering or equivalent.
• 3+ years of silicon PVT validation or high-volume manufacturing testing experience.
• Hands-on lab experience with silicon bring-up, lab debug, shmoo analysis, VF characteristics, test content bring-up, and correlation to Si characterization, yield, and coverage optimization.

Responsibilities

• Develop and implement robust closed-loop analysis for VF characteristics and POR expectations for MFG screening diagnostics.
• Support VF/VMIN/VMAX/PVT spec validation and productization across Manufacturing teams.
• Collaborate with HW engineering teams to determine test coverage and constraints for high-volume manufacturing screens.
• Assist prototyping and fine-tune speed, power, circuits, yield, and silicon coverage in SLT socketed environment.
• Coordinate SLT/BLT testing flows and translate learnings into shift-left improvements.
• Drive process improvements through root cause analysis and data analytics.

Skills

Data analysis

Lab debugging

Problem solving

Python

Education

Bachelor's or Master's degree in Microelectronics/Electrical/Electronic/Computer Engineering

Tools

BASH

Linux

Scripting

Job description

NVIDIA's Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first-principles thinking and engineering judgment at the highest level translate directly into product outcomes at scale. Our team gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production.

What you will be doing:

• Responsible for developing and implementing robust closed-loop analysis for VF characteristics and POR expectations vs. production screens to improve overall quality of MFG screening diags.
• Support VF/VMIN/VMAX/PVT spec validation and productization activities across Manufacturing teams and product segments.
• Partner multi-functionally with HW engineering teams such as Silicon PVT design and characterization teams, IO design and validation teams, system feature owners, SLT and BLT Production Operations, etc., to determine test coverage and constraints to resolve appropriate SLT/BLT test conditions, test content, and flows for high-volume manufacturing screens.
• Support prototyping and fine-tune speed, power, circuits, yield, and quality for effective silicon coverage in the SLT socketed environment.
• Support procedures to facilitate Silicon correlation activities between production testing infrastructure and internal Si characterization and diagnostics programs.
• Coordinate, develop, and maintain SLT/BLT testing flows, incorporating takeaways from silicon and correlating them to design for shift-left improvements.
• Initiate and drive process improvements and preventative actions through root cause analysis and data analytics.
• Partner with SW and platform teams to support and improve SLT testing infrastructure, debug knobs, and data collection features needed to support manufacturing screens effectively.

What we need to see:

• Bachelor's or Master's Degree or equivalent in Microelectronics/Electrical/Electronic/Computer Engineering or equivalent experience.
• 3+ years of relevant industry experience in silicon Post-silicon PVT validation and/or high-volume manufacturing testing for complex SoCs, GPUs, CPUs, or similar.
• Hands-on lab experience with silicon bring-up, lab debug, shmoo analysis, VF characteristics, test content bring-up, and correlation to Si characterization, yield, and coverage optimization.
• Strong EE fundamentals, device physics, knowledgeable in Silicon design, statistics, STA concepts, fault analysis, sampling, and computer architecture.
• Strong data analysis skills, a learning attitude, and prior experience working with large volumes of data.
• Prior understanding of manufacturing test strategy for a major silicon product (e.g., GPU/SoC/CPU) from early planning through ramp to QS/production is a plus.
• Good understanding of firmware/driver structures and their interaction with HW.
• Problem-solving, debugging, analysis, and logical reasoning skills with examples to prove it.
• Experience with Python, BASH, Linux, and scripting.

Ways to stand out above the crowd:

• Exceptional work ethic and up-leveling discussions to solve real problems
• Native use of AI tools to accelerate production testing and debug workflows
• Battle-tested/Exposed on GPUs, CPUs, AI accelerators, or other large-scale SoCs - you've seen firsthand how complexity at scale reshapes the failure landscape and demands a different level of engineering intuition.
• Supported multi-functional alignment on production methodologies adopted by other teams in a High Volume Manufacturing(HVM) environment.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.

• You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 1, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.