Lead Silicon Verification Architect

Hewlett Packard Enterprise; Sunnyvale (CA); On-site; USD 174,000 - 352,500; Full time

Benefits offered by this job

Health benefits

Career development

Inclusive culture

Job summary

Hewlett Packard Enterprise is seeking a Design Verification Manager to lead a world-class verification team for high-performance semiconductor products. The role spans defining verification strategy, architecture, and testing across block, sub-system, and full-chip levels, ensuring on-time tape-outs and high-quality silicon.

You will mentor engineers, drive automated flows, and collaborate with Architecture, RTL, Physical Design, and Post-Silicon teams to resolve coverage gaps and achieve

Qualifications

• 10+ years in pre-silicon ASIC/SoC design verification.
• 5+ years engineering leadership managing headcount and delivery.
• Proven UVM testbenches built from scratch and architecture ownership.

Responsibilities

• Lead and mentor a team of design verification engineers.
• Define global verification strategies and testbench architecture.
• Drive industry-standard methodologies and automation across projects.
• Collaborate with Architecture, RTL Design, Physical Design, and Post-Silicon teams to meet tape-out milestones.

Skills

SystemVerilog

UVM

Formal verification

Leadership

Testbench design

Education

Bachelor's degree in Electrical Engineering / Computer Science / Computer Engineering

Tools

Palladium

Zebu

Veloce

PCIe Gen6/7

CXL

HBM3

NVLink

Job description

Hewlett Packard Enterprise is seeking a Design Verification Manager to lead a world-class verification team for high-performance semiconductor products. The role spans defining verification strategy, architecture, and testing across block, sub-system, and full-chip levels, ensuring on-time tape-outs and high-quality silicon.

You will mentor engineers, drive automated flows, and collaborate with Architecture, RTL, Physical Design, and Post-Silicon teams to resolve coverage gaps and achieve