Lead RTL Design Engineer: AI Silicon Tapeout

Normal Computing Corporation; Palo Alto (CA); On-site; USD 180,000 - 250,000; Full time

Job summary

Normal Computing is seeking a Lead RTL Design Engineer to head RTL development for thermodynamic hardware. You will own RTL from microarchitecture to tapeout, write SystemVerilog, and guide verification and physical design to meet timing and area goals.

As a senior leader, you will shape architecture, refine design methodology, and drive cross‑functional alignment with architects, verification, and PD, while helping hire and mentor the team in a fast‑paced, collaborative environment.

Qualifications

• Led RTL design teams through tapeouts and design closure.
• Proven ability to deliver synthesizable SystemVerilog across datapath, control, and memory interfaces.
• Strong debugging instincts across simulations, waveforms, and formal methods.

Responsibilities

• Organize and lead the RTL design team with high expectations.
• Write and own synthesizable RTL in SystemVerilog across blocks.
• Translate microarchitectures into implementable RTL and collaborate with architecture.

Skills

RTL design

SystemVerilog

Team leadership

Debugging

Architecture collaboration

Tools

EDA tooling

Tapeout experience

Job description

Normal Computing is seeking a Lead RTL Design Engineer to head RTL development for thermodynamic hardware. You will own RTL from microarchitecture to tapeout, write SystemVerilog, and guide verification and physical design to meet timing and area goals.

As a senior leader, you will shape architecture, refine design methodology, and drive cross‑functional alignment with architects, verification, and PD, while helping hire and mentor the team in a fast‑paced, collaborative environment.