RTL Design Tech Lead | Remote + Equity, Tapeout Expert

MRL Consulting Group; California; On-site; USD 220,000 - 250,000; Full time

Benefits offered by this job

Fully covered medical, dental, and vision insurance

Equity

401(k) matching

Work-from-home hardware support

Job summary

MRL Consulting Group Ltd. is looking for an experienced RTL Design Tech Lead to join their semiconductor startup in California. This role focuses on driving technical execution of microarchitecture and RTL development for advanced ASIC/SoC programs, emphasizing high-quality design and collaboration.

Candidates should have over 10 years of experience in RTL design, strong expertise in SystemVerilog, and a proven track record of successful project leadership. Benefits include competitive compensation, comprehensive health coverage, and equity opportunities.

Qualifications

• 10+ years of ASIC/SoC RTL design experience.
• Strong background in SystemVerilog and microarchitecture development.
• Experience leading successful tapeouts and debugging silicon issues.

Responsibilities

• Drive microarchitecture and RTL development for ASIC/SoC programs.
• Mentor engineers and conduct design reviews.
• Ensure high RTL quality through various compliance checks.

Skills

ASIC/SoC RTL design experience

SystemVerilog/Verilog expertise

Microarchitecture development

Timing analysis

Low-power design

Scripting in Python or Tcl

Job description

A semiconductor startup based in Sunnyvale, CA is building next-generation graphics processors focused on maximizing performance and efficiency. The company takes a first-principles approach to engineering and is driven by a mission to reduce the barriers to creating, simulating, and consuming immersive digital experiences. Its culture emphasizes fearlessness, adaptability, and selfless collaboration in pursuit of ambitious technical goals.

The team is seeking an experienced RTL Design Tech Lead to drive microarchitecture, RTL development, and technical execution across complex ASIC/SoC programs from architecture through tapeout. This role combines deep hands-on design expertise with leadership responsibilities, including mentoring engineers, driving design reviews and coding standards, collaborating cross-functionally with DV, PD, STA, and DFT teams, and ensuring high RTL quality through lint, CDC/RDC, low-power compliance, and silicon bring-up debugging.

Candidates should have 10+ years of ASIC/SoC RTL design experience, strong expertise in SystemVerilog/Verilog, microarchitecture development, timing analysis, CDC/RDC methodologies, low-power design, and synthesis flows. Experience leading multiple successful tapeouts, debugging complex silicon issues, and operating effectively under aggressive schedules is essential. Preferred qualifications include advanced-node experience (12FFC, 7nm, 5nm), GLS expertise, DFT knowledge, familiarity with high-speed IPs such as DDR or PCIe, scripting in Python or Tcl, and experience working with foundries like TSMC in startup or first-silicon environments.

This role requires a strong ownership mindset and the ability to balance individual technical contribution with team leadership. The Tech Lead will provide architectural guidance, mentor engineers, influence cross-functional decisions, and maintain high standards for engineering execution and design quality. Compensation ranges from $220,000–$250,000 annually in California, with benefits including fully covered medical, dental, and vision insurance, equity, 401(k) matching, and work-from-home hardware support.