Signal Integrity Engineer: High-Speed AI/Cloud Hardware

SYNNEX Corporation; Fremont (CA); On-site; USD 99,000 - 130,000; Full time

Benefits offered by this job

401(k) with company match

Health insurance

HSA

FSA

Paid holidays

Job summary

Hyve Solutions seeks a Signal Integrity Engineer to tackle pre- and post-layout SI for high-speed interfaces, including PCIe, CXL, Ethernet, SerDes, and DDR5/DDR6. You will model channels, develop stackups, and assist with lab validation using HFSS, HSPICE, Sigrity and CST.

You will collaborate with hardware design and PCB teams to ensure SI best practices, participate in EVT/DVT/PVT bring-up, and help produce SI guidelines and reports for product releases.

Qualifications

• Bachelors or Masters in Electrical Engineering or related field.
• 2–5 years in Signal Integrity / High-Speed Digital Design or related.
• Experience with channel simulation, high-speed interfaces, or lab measurements desired.
• Familiarity with transmission line theory and high-speed channel design.

Responsibilities

• Perform pre-layout and post-layout signal integrity simulations for PCIe, CXL, Ethernet, SerDes, and DDR5/DDR6.
• Develop channel models using HFSS, ADS, HSPICE, Sigrity or similar tools.
• Support lab validation with oscilloscopy, VNA, TDR, and BER testing; correlate with simulations.
• Collaborate with HW design and PCB layout teams to implement SI best practices.
• Document methodologies and findings; contribute to SI design guidelines.

Skills

Signal Integrity

High-Speed Design

Electromagnetic Theory

PCB Stackups

SI Simulation

Education

Bachelor's or Master's in Electrical Engineering

Tools

HFSS

ADS

HSPICE

Sigrity

CST

VNA

Job description

Hyve Solutions seeks a Signal Integrity Engineer to tackle pre- and post-layout SI for high-speed interfaces, including PCIe, CXL, Ethernet, SerDes, and DDR5/DDR6. You will model channels, develop stackups, and assist with lab validation using HFSS, HSPICE, Sigrity and CST.

You will collaborate with hardware design and PCB teams to ensure SI best practices, participate in EVT/DVT/PVT bring-up, and help produce SI guidelines and reports for product releases.