Signal Integrity Engineer - High-Speed HW, Hybrid Role

Hyve Solutions; Fremont (CA); Hybrid; USD 99,000 - 130,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

401(k) with company match

FSA

HSA

Paid holidays

Job summary

Hyve Solutions is seeking a Signal Integrity Engineer to join our hybrid office and lab in the United States. You will perform pre-layout and post-layout SI simulations for PCIe, CXL, Ethernet, SerDes, and DDR5/DDR6, supporting design through validation.

Collaborating with hardware design and PCB layout teams, you will develop channel models using HFSS/ADS/HSPICE/Sigrity, and assist with validation, compliance testing, and documentation.

Qualifications

• Experience with channel simulation and high-speed interfaces.
• Strong analytical and troubleshooting skills.
• Excellent written and verbal communication and teamwork.

Responsibilities

• Perform pre-layout and post-layout signal integrity simulations for PCIe, CXL, Ethernet, SerDes, and DDR5/DDR6.
• Analyze channel performance, insertion loss, return loss, crosstalk, and timing margins to support robust design.
• Develop and execute channel models using industry tools such as HFSS, ADS, HSPICE, Sigrity, or comparable environments.
• Support stackup development, impedance control, and routing rules for high-speed PCBs.
• Assist with connector, cable, package, and channel characterization activities.
• Collaborate with hardware design and PCB layout engineers to ensure SI best practices and design guidelines.
• Participate in EVT, DVT, and PVT bring-up activities and support debug efforts for SI issues.
• Maintain simulation reports, measurement results, and engineering documentation.

Skills

Signal integrity

High-speed design

Hardware engineering

Education

Bachelor's or Master's in Electrical Engineering

Tools

HFSS

ADS

HSPICE

Sigrity

CST

Job description

Hyve Solutions is seeking a Signal Integrity Engineer to join our hybrid office and lab in the United States. You will perform pre-layout and post-layout SI simulations for PCIe, CXL, Ethernet, SerDes, and DDR5/DDR6, supporting design through validation.

Collaborating with hardware design and PCB layout teams, you will develop channel models using HFSS/ADS/HSPICE/Sigrity, and assist with validation, compliance testing, and documentation.