Signal Integrity Engineer: AI HPC Packaging & SerDes

Ampere Computing LLC; Santa Clara, Northern (CA, KY); Hybrid; USD 159,000 - 239,000; Full time

Benefits offered by this job

Health insurance

401K plan

Unlimited flextime

Job summary

Ampere Computing LLC is seeking a Signal Integrity Engineer to join our team in Santa Clara, CA. You will collaborate with chip designers and hardware teams to ensure robust signal integrity and power integrity across packaging, PCB, and interconnects for high-performance AI compute products.

Responsibilities include simulating end-to-end high-speed DDR I/O and SerDes interfaces, modeling power delivery networks, and developing guidelines for PCB layout.

Qualifications

• Experience in design, simulation, measurement or validation in power integrity or signal integrity.
• Understanding of interconnect electrical behavior for high-speed signaling and power delivery.
• Experience developing electrical interconnect models (s-parameter, RLC) and using HFSS/PowerSI/PowerDC.
• Knowledge of SI/PI simulation methodologies and IBIS-AMI/I BIS models.

Responsibilities

• Collaborate with chip designers and hardware teams to ensure robust SI/PI across packaging and PCB.
• Simulate and analyze end-to-end high-speed DDR I/O and SerDes interfaces.
• Model and analyze power delivery networks in the package and PCB.
• Model channels for high-speed SerDes/DDR including package, PCB, vias, connectors, and sockets.
• Develop package-related PCB layout guidelines and documentation for internal and external customers.

Skills

Signal integrity

Power integrity

S-parameter models

IBIS/IBIS-AMI

HSPICE

Interconnect modeling

Education

PhD in Electrical Engineering or Computer Engineering

MS in Electrical Engineering or Computer Engineering

BS in Electrical Engineering or Computer Engineering

Tools

Ansys HFSS

PowerSI

PowerDC

Job description

Ampere Computing LLC is seeking a Signal Integrity Engineer to join our team in Santa Clara, CA. You will collaborate with chip designers and hardware teams to ensure robust signal integrity and power integrity across packaging, PCB, and interconnects for high-performance AI compute products.

Responsibilities include simulating end-to-end high-speed DDR I/O and SerDes interfaces, modeling power delivery networks, and developing guidelines for PCB layout.