Senior Signal Integrity Engineer

EngineersOfAI; Austin (TX); On-site; USD 110,000 - 135,000; Full time

Job summary

EngineersOfAI in Austin, Texas, is looking for a Senior Signal Integrity Engineer to develop and optimize high-speed signaling solutions across blade- and rack-level architectures. The ideal candidate will have a strong background in signal integrity and hands-on measurement expertise.

This role involves collaboration with cross-functional engineering teams to analyze and validate high-speed I/O interfaces, ensuring optimal system performance. The position offers competitive compensation and opportunities for professional growth.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong experience in signal integrity for high-speed digital systems.
• Hands-on measurement expertise using VNAs, TDRs, BERTs, and high-speed oscilloscopes.

Responsibilities

• Conduct end-to-end signal integrity analysis for blade- and rack-level system architectures.
• Analyze high-speed and low-speed I/O interfaces such as PCIe, Ethernet, and DDR.
• Perform simulations using state-of-the-art engineering tools.

Skills

Signal Integrity Analysis

High-Speed Interfaces (PCIe, Ethernet, DDR)

Hands-on Measurement Expertise

Simulation Correlation

Technical Communication

Education

Bachelor’s or Master’s in Electrical Engineering or related field

Tools

Ansys HFSS

Keysight ADS

Cadence Sigrity

CST

SPICE

VNA

TDR

BERT

High-speed oscilloscopes

Job description

About the Role

We are seeking a Senior Signal Integrity Engineer to develop, validate, and optimize high-speed signaling solutions across blade- and rack-level architectures for advanced compute platforms. This role sits at the intersection of silicon, package, interconnect, board, and system design, with a strong emphasis on hands‑on measurement, simulation correlation, and cross-functional technical communication.

Key Responsibilities

• End-to-end signal integrity analysis for blade- and rack-level system architectures.
• Analyze and optimize high-speed and low-speed I/O interfaces, including PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI, I2C, etc. and related interconnects.
• Perform time-domain and frequency-domain simulations using tools such as Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE, or similar.
• Support hands-on lab validation using VNA, TDR, BERT, and high-speed oscilloscopes.
• Correlate simulation results with lab measurements to identify margin gaps, debug issues, and improve design methodology.
• Collaborate with silicon, package, board, connector, cable, and system design teams to optimize I/O channel performance.
• Work with interconnect vendors and ODMs to guide board layout, stack-ups, routing rules, and system design decisions.
• Review schematics, layouts, simulation results, and validation data for blade, backplane, and rack-level hardware.
• Prepare and communicate clear validation reports, measurement summaries, debug findings, and technical recommendations to internal teams, vendors, and senior technical stakeholders.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong experience in signal integrity for high-speed digital systems.
• Hands‑on measurement expertise using VNAs, TDRs, BERTs, and high-speed oscilloscopes.
• Experience measuring and analyzing S-parameters, impedance profiles, eye diagrams, jitter, timing margins, insertion loss, return loss, and crosstalk.
• Knowledge of high-speed interfaces such as PCIe Gen4/5/6, Ethernet, DDR, SerDes, and related I/O technologies.
• Experience with SI/PI simulation tools such as HFSS, ADS, Sigrity, CST, SPICE, or equivalent.
• Ability to correlate lab measurements with simulations and use data to guide design decisions.
• Strong communication skills, including the ability to produce clear validation reports, present technical findings, and work effectively across multi‑functional engineering teams.

Preferred Qualifications

• Experience in hyperscale, data center, cloud infrastructure, or advanced compute hardware environments.
• Experience with blade, backplane, board-to-board, cable, or rack-level interconnect architectures.
• Knowledge of thermal and mechanical considerations that impact SI/PI performance.
• Experience with calibration, de-embedding, fixture design, lab automation, or measurement methodology development.
• Experience using Python, MATLAB, or similar scripting languages for simulation automation, measurement automation, and data analysis.

Tools / Technologies

Measurement: VNA, TDR, BERT, high-speed oscilloscopes
Simulation: Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE
Interfaces: PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI, high-speed interconnects
Analysis: S-parameters, eye diagrams, jitter, timing margins, impedance control, crosstalk, insertion loss, return loss, de-embedding, measurement-to-simulation correlation