Signal Integrity Engineer

USA Tech Recruit; Atlanta (GA); Presencial; USD 120.000 - 180.000; Jornada completa

Descripción de la vacante

USA Tech Recruit is seeking a seasoned SPE Signal Integrity Engineer in the United States to lead SI/PI and package design for memory interface chips, driving high-speed DDR technologies at 12800+ MT/s. The role demands deep expertise in SI/PI, high-speed SerDes, and lab validation.

The ideal candidate will have 10+ years of experience, MS/PhD in EE, and hands-on familiarity with DDR4/5, SPICE/ADS, and EM transmission line theory, reporting to an advanced engineering team.

Formación

• 10+ years of experience in signal integrity, power integrity and/or package design.

Responsabilidades

• Provide technical leadership across signal integrity, power integrity, package design and high-speed DDR technologies.
• Lead SI/PI activities across silicon, package, PCB, simulation and lab validation to deliver next-generation high-speed DDR technologies.

Conocimientos

Signal Integrity

Power Integrity

Package Design

DDR4/DDR5

SerDes interfaces

Lab measurements

Oscilloscope/TDR/VNA

Communication skills

Educación

MS or PhD in Electrical Engineering

Herramientas

ADS

HFSS

Q3D/PowerSI

Virtuoso

RedHawk/Totem

XcitePI

APD/Allegro

Descripción del empleo

A leading semiconductor and silicon IP company is seeking an experienced SPE Signal Integrity Engineer to join its Memory Interface Chips business unit. The role will provide technical leadership across signal integrity, power integrity, package design, and high-speed DDR technologies operating at speeds of 12800+ MT/s.

The ideal candidate will have 10+ years of industry experience with strong SI/PI and package design expertise, including hands-on experience with DDR4/5 or high-speed SerDes interfaces.

The key skills required for the SPE Signal Integrity Engineer:

• 10+ years’ industry experience in signal integrity, power integrity and/or package design
• MS or PhD in Electrical Engineering
• Strong experience with DDR4/DDR5 and/or high-speed SerDes interfaces
• Deep understanding of electromagnetic and transmission line theory
• Experience with equalisation techniques including FIR, FFE, DFE and CTLE
• Strong package and PCB design experience, including APD/Allegro
• Experience with BGA assignment and SI/PI-driven package and PCB design
• Strong channel simulation, jitter, crosstalk and low-BER analysis experience
• Experience correlating simulations with lab measurements using oscilloscopes, TDRs and VNAs
• Proficiency with SPICE and ADS simulation
• Experience with EDA tools such as ADS, HFSS, Q3D/PowerSI
• Familiarity with RedHawk/Totem, XcitePI or Virtuoso desirable
• Experience with lab characterization, link margin and noise measurements beneficial
• Understanding of server systems, CPUs, DRAM and DIMM modules desirable
• Strong communication, presentation and technical writing skills

This is an excellent opportunity to take a highly visible technical leadership role within an advanced memory interface engineering team, working across silicon, package, PCB, simulation and lab validation to deliver next-generation high-speed DDR technologies.

Key words: Signal Integrity / SI / Power Integrity / PI / DDR4 / DDR5 / SerDes / High Speed / Package Design / PCB / BGA / APD / Allegro / Transmission Lines / EM / Equalization / FIR / FFE / DFE / CTLE / Crosstalk / Jitter / Low BER / SPICE / ADS / HFSS / Q3D / PowerSI / RedHawk / Totem / XcitePI / Virtuoso / VNA / TDR / Oscilloscope / Memory Interface / DRAM / DIMM / Semiconductor

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