Senior DDR SI/PI Engineer — High-Speed Memory

Usatech Recruit; United States; On-site; USD 150,000 - 230,000; Full time

Job summary

Usatech Recruit is seeking a SPE Signal Integrity Engineer to lead SI/PI studies for DDR4/5 designs. You will model, analyze, and simulate SI/PI performance, define package and PCB requirements, and guide cross-functional teams to optimize channel performance.

The role requires a strong background in EM, transmission line theory, and advanced equalization techniques, with extensive lab correlation and collaboration with customers. Prior DDR4/5 experience is essential.

Qualifications

• MS or PhD in Electrical Engineering with 10+ years of industry experience (DDR4/5).
• Solid background in SI/PI and package design providing technical leadership.

Responsibilities

• Create SI/PI methodologies and work with Design and SI teams for SI/PI study and package design for the latest DDR product portfolio.
• Define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis.
• Provide guidelines to design team based on SI/PI study and simulation and silicon correlation to achieve superior SI performance (RMT scores).
• Collaborate with customers to find optimum SI/PI solutions.
• Assist the team during debug and lab bring-up as needed.

Skills

SI/PI leadership

Interpersonal skills

High-speed memory simulations

EM/transmission line theory

Equalization techniques

Package/PCB design

Lab correlation methods

Server systems knowledge

Crosstalk & jitter

Spice/ADS

EDA tools

EDA tool familiarity

Lab characterization

High-speed link circuits

Communication skills

Project teamwork

Education

MS or PhD in Electrical Engineering

Tools

ADS

HFSS

Q3D/PowerSI

Virtuoso

Spice

Job description

Usatech Recruit is seeking a SPE Signal Integrity Engineer to lead SI/PI studies for DDR4/5 designs. You will model, analyze, and simulate SI/PI performance, define package and PCB requirements, and guide cross-functional teams to optimize channel performance.

The role requires a strong background in EM, transmission line theory, and advanced equalization techniques, with extensive lab correlation and collaboration with customers. Prior DDR4/5 experience is essential.