Senior DDR4/DDR5 Signal Integrity Engineer

Protingent

Johns Creek (GA)

Hybrid

USD 134,000 - 288,000

Full time

5 days ago
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Job summary

Protingent is seeking an experienced SPE Signal Integrity Engineer in Johns Creek, GA. You will lead SI/PI methodologies and collaborate with design and validation teams to define packaging, routing, and decoupling requirements for DDR4/5 products.

You will guide the design team on SI/PI outcomes and help customer collaborations to optimize solutions. Requires 10+ years in SI/PI with DDR memory experience, strong EM theory, and proficiency in Spice/ADS simulations and relevant EDA tools.

Qualifications

  • Strong SI/PI and package design leadership
  • Experience with DDR4/5 as needed
  • Proficiency in EM and transmission line theory
  • FIR/FFE/DFE/CTLE equalization knowledge
  • Ability to edit APD/Allegro layout files
  • Familiarity with correlating simulation to lab measurements.
  • Server system knowledge from CPUs to DIMMs is a plus

Responsibilities

  • Create SI/PI methodologies and work with Design and SI teams for DDR product studies and package design
  • Define specs and system design requirements including packaging and PCB routings, IC-PKG-BRD decoupling, channel simulations and jitter analysis
  • Provide guidelines based on SI/PI study and silicon correlation to achieve superior SI performance
  • Collaborate with customers to identify optimal SI/PI solutions
  • Assist team during debug and lab bring-up

Skills

SI/PI
Package design
EM theory
Transmission line theory
Equalization (FIR/FFE/DFE/CTLE)
High-speed memory/SERDES
Lab measurement correlation
Circuit editing (APD/Allegro)
Spice/ADS simulations
EDA tools (ADS/HFSS/Q3D/PowerSI)
Virtuoso familiarity

Education

MS or PhD in Electrical Engineering

Tools

ADS
HFSS
Q3D/PowerSI
Virtuoso
RedHawk/Totem
XcitePI

Job description

Protingent is seeking an experienced SPE Signal Integrity Engineer in Johns Creek, GA. You will lead SI/PI methodologies and collaborate with design and validation teams to define packaging, routing, and decoupling requirements for DDR4/5 products.

You will guide the design team on SI/PI outcomes and help customer collaborations to optimize solutions. Requires 10+ years in SI/PI with DDR memory experience, strong EM theory, and proficiency in Spice/ADS simulations and relevant EDA tools.

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