SPE Signal Integrity Engineer

Rambus.com; Johns Creek (GA); On-site; USD 133,900 - 248,700; Full time

Benefits offered by this job

Base salary

Bonus

Equity

Matching 401(k)

Comprehensive medical and dental benefits

Time-off program

Gym membership

Job summary

Rambus.com, a leader in chip and silicon IP solutions, is seeking a Sr. Principal Engineer in Johns Creek, Georgia. This position focuses on signal integrity and package design within the memory interface chips team.

The ideal candidate will foster collaboration across teams, contribute to product designs, and ensure superior performance in high-speed memory systems like DDR4 and DDR5. A strong educational background in Electrical Engineering and substantial experience in simulation and analysis techniques are required.

Rambus offers a competitive compensation package, with salaries ranging from $133,900 to $248,700 based on experience and qualifications.

Qualifications

• 10+ years of industry experience, with exposure to DDR4/5.
• Experience in simulating high-speed memory (DDR4, DDR5).
• Ability to edit APD/Allegro layout files.

Responsibilities

• Create SI/PI methodologies for DDR product portfolio.
• Define specifications and system design requirements.
• Collaborate with customers for optimal SI/PI solutions.

Skills

Signal Integrity expertise

Package design

Interpersonal skills

Electrical Engineering background

Simulation proficiency

Understanding of equalization techniques

Education

MS or PhD in Electrical Engineering

Tools

Spice

ADS

HFSS

Q3D/PowerSI

Job description

Overview

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Sr. Principal Engineer with signal integrity and package design experience to join our Memory Interface Chips BU’s engineering team in John's Creek, Georgia. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

As an SPE Signal Integrity Engineer, you will be reporting to the VP of Engineering and is a Full Time position. In this highly visible role, you will work within our SI/PI team to work on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) in the very challenging DDR field with speed up to 12800+ MT/s.

Responsibilities

• Create SI/PI methodologies and work with the Design and SI teams to do SI/PI study and package design for the latest DDR product portfolio
• Work with our design team and validation team to define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis
• Provide guideline to design team based on SI/PI study and simulation and silicon correlation so that our products will have superior SI performance, i.e. best RMT scores
• Work with our customers to do collaboration to find the optimum SI/PI solution
• Help the team during debug and bring up in lab if needed

Qualifications

• Solid background in SI/PI and package design to provide technical leadership to the team
• Strong interpersonal skill to keep the team motivated and focused
• MS or PhD in Electrical Engineering with 10+ years of industry experience in which at least a few years with exposure to DDR4/5
• Prior experience in simulating high speed memory (DDR4, DDR5) and/or SERDES interfaces is required
• Solid theoretical background and understanding in EM and transmission line theory is a must
• Strong background and solid understanding of equalization techniques such as FIR/FFE/DFE/CTLE are required
• Must understand package and PCB design, be able to edit APD/Allegro layout files. Know SI/PI driven BGA assignment methodology and be able to simulate for the trade-offs in the context of a system
• Extensive experience in correlating simulation results with lab measurements using scopes, TDRs, VNAs etc.
• Strong understanding of the server system, from CPUs to DRAMs on DIMM modules, is highly desirable
• Know the mechanisms of crosstalk and jitter in source-synchronous interfaces and be able to include the effect of such losses into low BER simulations
• Proficient with simulations using Spice and ADS
• Experience with commercial EDA tools such as ADS, HFSS, Q3D/PowerSI
• Familiarity with RedHawk/Totem or XcitePI and Virtuoso is a strong plus
• Lab characterization experience of passive components, link margin, or noise using real time/sampling scopes and VNA/TDR is a big plus
• Basic knowledge of circuits used in high-speed link design is preferred.
• Excellent writing and presentation skills are essential as well as good communication skills to work with customers and cross-functional teams.
• Must be an innovative, self-motivated individual, be able to manage and drive his projects, and must be a team player

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time‑off program, and gym membership. The US- John's Creek, GA salary range for this full‑time position is $133,900 to $248,700. Our salary ranges are determined by role, level and location. The successful candidate’s starting pay will be determined based on job‑related skills, experience, qualifications, work location and market conditions.

Rambus is proud to be an Equal Employment Opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application.