IC Package Layout Engineer — 2.5D/3D-IC Specialist

Amazon Web Services (AWS); Cupertino (CA); On-site; USD 157,000 - 213,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. in Cupertino, CA is seeking a Package Layout Design Engineer to drive advanced IC package layouts from floor planning through tape-out. You will partner with ASIC teams, SI/PI, and manufacturing to meet density, performance and reliability targets.

The role requires hands-on experience with packaging tools, 2.5D/3D-IC packaging, RDL/substrate routing, and rigorous DFM/verification to ensure production-ready designs for next‑gen ML and data center ASICs.

Qualifications

• Bachelor's degree in Electrical Engineering or related field; 5+ years of IC package layout experience.
• Experience executing package designs from concept through tape-out for multi-layer substrates or interposers.
• Hands-on with package layout tools (Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition).
• Understanding of 2.5D/3D-IC, fan-out WLP, RDL, TSV, microbumps, or silicon bridge interconnects.
• Knowledge of DFM constraints, design rules, and physical verification methods (DRC, connectivity).
• Ability to collaborate with SI/PI, electrical teams, and manufacturing.

Responsibilities

• Execute package layout tasks across the design cycle (die floor planning, bump/pad assignment, RDL routing, substrate design, tape-out release).
• Implement physical designs for 2.5D/3D-IC packaging architectures (CoWoS/EMIB or similar).
• Support floorplan development with die placement, power/ground, and decoupling considerations.
• Perform high-density interconnect routing (RDL, substrate) including microbumps and TSVs.
• Coordinate with ASIC teams to co-optimize die-package interfaces and cross-level layout.
• Conduct design verification checks and help ensure DFM/compliance.

Skills

Package layout

IC packaging

2.5D/3D-IC

RDL routing

Power/ground design

DFM constraints

DRC verification

cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical or related field

Tools

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

OSAT collaboration

Job description

Annapurna Labs (U.S.) Inc. in Cupertino, CA is seeking a Package Layout Design Engineer to drive advanced IC package layouts from floor planning through tape-out. You will partner with ASIC teams, SI/PI, and manufacturing to meet density, performance and reliability targets.

The role requires hands-on experience with packaging tools, 2.5D/3D-IC packaging, RDL/substrate routing, and rigorous DFM/verification to ensure production-ready designs for next‑gen ML and data center ASICs.