Senior SI/PI Engineer for AI Silicon Packaging

Amazon

Austin (TX)

On-site

USD 159,000 - 215,000

Full time

11 days ago

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Job summary

Annapurna Labs, an AWS division within Amazon, seeks a Sr. Signal & Power Integrity Engineer to own package-level SI/PI strategy for 2.5D/3D-IC, fan-out, and interposer architectures used in AI silicon packaging.

You will drive design closure, simulations, and measurements across die, package, and board interfaces to meet performance and manufacturing targets. With 10+ years in SI/PI and package design, you will correlate simulations with lab data (TDR, VNA, oscilloscope), collaborate with ASIC

Qualifications

Bachelor's degree in Electrical Engineering or related field.
10+ years of experience in signal integrity, power integrity, and package design.
Deep expertise in package SI/PI analysis: S-parameter extraction, PDN impedance analysis, IR drop, crosstalk, and return loss.
Hands-on experience with EM simulation and SI/PI tools such as HFSS, Cadence Sigrity (PowerSI, PowerDC, Clarity), ADS, or equivalent.
Strong understanding of advanced packaging technologies: 2.5D/3D-IC, silicon interposers, fan-out wafer-level packaging, RDL, TSVs, and microbump interconnects.
Experience analyzing and modeling decoupling technologies including on-die MOM/MOS capacitors, deep trench capacitors (DTCs), and IPD capacitors within the package PDN.
Proficiency in stack-up design and impedance control for multi-layer organic substrates and silicon interposers.
Hands-on experience correlating package SI/PI simulations with lab measurements (TDR, VNA, oscilloscope).

Responsibilities

Lead package-level SI/PI analysis for 2.5D, 3D-IC, fan-out, and silicon interposer/bridge architectures.
Design and optimize package stack-ups: dielectric material selection, impedance control, layer assignment, and RDL routing for high-speed and power delivery performance.
Perform high-speed channel simulations (S-parameter extraction, time-domain analysis, eye diagrams) for die-to-die and die-to-board interfaces through the package.
Analyze and optimize the package PDN end-to-end: decoupling strategy, plane resonance, IR drop, and AC impedance from die bumps through substrate to board.
Characterize and model on-die capacitance, deep trench capacitors (DTCs), and IPD capacitors; evaluate their effectiveness within the full-stack PDN impedance profile.
Interface with SoC die-level PDN teams to align power grid requirements, current profiles, and decoupling budgets across the chip-package boundary.
Perform 3D/2.5D EMIR analysis using tools such as Ansys RedHawk-SC 3DIC, Cadence Voltus, or equivalent to validate IR drop and electromigration across multi-die stacked packages.
Model advanced interconnects: microbumps, C4 bumps, TSVs, microvias, PTH vias, and RDL traces for both signal and power paths.
Apply equalization techniques (DFE, CTLE, FFE) and evaluate package-level channel margins for PCIe, UCIe, and custom die-to-die links.
Perform clock distribution and jitter analysis at the package level, accounting for coupling, skew, and return path discontinuities.
Collaborate with ASIC design, board design, and packaging/assembly teams to co-optimize package architecture for electrical performance and manufacturing yield.
Identify and mitigate package manufacturing risks — warpage, via reliability, impedance variation, and material tolerance impacts on SI/PI.
Develop and maintain package SI/PI modeling flows, automation scripts, and design guidelines.