Senior Wireless MAC Verification Engineer

Apple, Inc.; Sunnyvale (CA); On-site; USD 185,000 - 325,000; Full time

Job summary

Apple is seeking a Wireless MAC Design Verification Engineer to join its wireless silicon team in Sunnyvale. You will perform pre-silicon RTL verification of the MAC and its interfaces, collaborating with DV methodologists, designers, and systems engineers to build reusable test benches and robust verification environments with metric-driven approaches.

Responsibilities include developing directed and constrained-random tests, managing bugs, creating coverage models, and driving issues to

Qualifications

• BS and a minimum of 10 years relevant industry experience.
• Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
• Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
• Verification experience of one or more: MAC, PHY, DMA, timer, AMBA bus and fabric, encryption/decryption engine.

Responsibilities

• Review MAC subsystem microarchitecture and create verification plan from specification.
• Build block/subsystem level test benches and create reusable UVM libraries.
• Develop and run directed and constrained random tests, debug failures, and close issues with designers.
• Create and analyze block/subsystem coverage models and extend coverage.
• Apply ML techniques to identify design and test bench issues and improve DV quality.

Skills

Verilog

SystemVerilog

UVM

SVA

MAC

PHY

AMBA

Python

Shell

Education

BS in Electrical Engineering

Tools

Palladium

FPGA

Job description

Apple is seeking a Wireless MAC Design Verification Engineer to join its wireless silicon team in Sunnyvale. You will perform pre-silicon RTL verification of the MAC and its interfaces, collaborating with DV methodologists, designers, and systems engineers to build reusable test benches and robust verification environments with metric-driven approaches.

Responsibilities include developing directed and constrained-random tests, managing bugs, creating coverage models, and driving issues to