Wireless MAC Verification Engineer - RTL/UVM Expert

Apple Inc.; San Diego (CA); On-site; USD 123,000 - 214,000; Full time

Benefits offered by this job

Comprehensive medical and dental cover

Employee stock purchase plan

Discretionary bonuses/commissions

Tuition reimbursement

Relocation assistance

Job summary

Apple Inc. is seeking a Wireless Design Verification Engineer in San Diego, CA to drive pre-silicon RTL verification of the wireless MAC and its interfaces within the SoC.

You'll collaborate with DV teams to create reusable testbenches, develop constrained-random tests, and push coverage targets using metric-driven techniques. You will apply Verilog/SystemVerilog/UVM expertise, work with Palladium/FPGA validation, and contribute to DV methodology improvements.

Qualifications

• Bachelor's degree in a relevant engineering field.
• Advanced knowledge of Verilog, SystemVerilog, UVM, and SVA.
• Experience with ASIC verification flows and test bench development.
• Experience in MAC/PHY/DMA/Wireless subsystems preferred.

Responsibilities

• Review MAC subsystem microarchitecture with system and design teams; create a verification plan from specification and refine to meet coverage targets.
• Build block/subsystem testbenches and create UVM libraries; architect reusable test benches.
• Develop and execute directed and constrained random tests; debug failures and drive issue closure.
• Create and analyze block/subsystem coverage models and add test cases to increase coverage.
• Apply machine learning/AI to identify DV issues and improve DV quality.
• Support MAC validation using Palladium and/or FPGA; collaborate to improve DV methodology and flow.

Skills

Verilog

SystemVerilog

UVM

SVA

ASIC verification

MAC/PHY/DMA

Education

Bachelor's degree in a related field

Tools

Python scripting

Shell scripting

Palladium FPGA

Job description

Apple Inc. is seeking a Wireless Design Verification Engineer in San Diego, CA to drive pre-silicon RTL verification of the wireless MAC and its interfaces within the SoC.

You'll collaborate with DV teams to create reusable testbenches, develop constrained-random tests, and push coverage targets using metric-driven techniques. You will apply Verilog/SystemVerilog/UVM expertise, work with Palladium/FPGA validation, and contribute to DV methodology improvements.