Senior Wireless MAC DV Engineer – SoC Verification

Apple, Inc.; San Diego (CA); Presencial; USD 175.000 - 309.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical & dental

Stock programs

Relocation assistance

Education reimbursement

Discounted products

Descripción de la vacante

Apple Inc. invites you to join its wireless silicon development team as a Wireless MAC Design Verification Engineer.

You will be at the center of a silicon design group, performing pre-silicon RTL verification of the MAC and its interfaces, collaborating with DV methodologists, designers, and systems engineers. You will build reusable test benches, develop directed and constrained random tests, analyze coverage, and use AI to identify issues.

Formación

• BS and at least 10 years of relevant industry experience.
• Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
• Experience with ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
• Verification experience of MAC, PHY, DMA, timer, AMBA bus and fabric, encryption/decryption engine.

Responsabilidades

• Review MAC subsystem microarchitecture and create verification plan to achieve coverage targets.
• Build block/subsystem level test benches and UVM libraries with reusable design.
• Develop and execute directed and constrained random tests, debug and track defects.
• Create and analyze coverage models and add tests to increase coverage.
• Use machine learning/AI to identify DV issues and improve quality.
• Support MAC validation using Palladium and/or FPGA.
• Improve DV methodology and flow with team.

Conocimientos

Verilog

SystemVerilog

UVM

Code coverage

Constrained random

Test benches

Python

Shell scripting

Perl scripting

Machine learning

Educación

BS in Electrical/Computer Engineering

Herramientas

Palladium

FPGA

Verilog

SystemVerilog

Descripción del empleo

Apple Inc. invites you to join its wireless silicon development team as a Wireless MAC Design Verification Engineer.

You will be at the center of a silicon design group, performing pre-silicon RTL verification of the MAC and its interfaces, collaborating with DV methodologists, designers, and systems engineers. You will build reusable test benches, develop directed and constrained random tests, analyze coverage, and use AI to identify issues.