Senior Wireless MAC Verification Engineer

Apple Inc.; California; On-site; USD 175,000 - 309,000; Full time

Job summary

Apple Inc. is seeking a Wireless MAC Design Verification Engineer to join its wireless silicon development team in California.

You will perform pre-silicon RTL verification of the wireless MAC and its interfaces, build reusable test benches, and drive coverage and quality with metric-driven verification across DV methods. You will collaborate with DV methodologists, designers, and systems engineers to deploy the latest verification techniques, including AI-assisted debugging, and you will

Qualifications

• BS and at least 10 years of relevant industry experience.
• Advanced knowledge of Verilog, SystemVerilog, UVM and SystemVerilog Assertions.
• Experience with ASIC verification flows: test bench development, constrained random testing, and coverage.
• Verification experience of MAC, PHY, DMA, timer, AMBA bus and fabric, or encryption/decryption engines.

Responsibilities

• Review MAC subsystem microarchitecture; create verification plan to meet coverage targets.
• Build block/subsystem level test benches; create reusable UVM libraries.
• Develop and run directed and constrained random tests; debug and drive issue closure.
• Create and analyze coverage models; add test cases to increase coverage.
• Use AI techniques to identify DV issues and improve quality.
• Support MAC validation using Palladium and/or FPGA; improve DV methodology.

Skills

Verilog

SystemVerilog

UVM

SystemVerilog Assertions

ASIC verification

Test benches

Constrained random testing

Coverage

MAC

PHY

DMA

AMBA bus

Encryption/Decryption

Embedded verification tooling

Education

BS in Electrical Engineering or related field

Tools

Palladium

FPGA

Shell scripting

Python scripting

Perl scripting

Job description

Apple Inc. is seeking a Wireless MAC Design Verification Engineer to join its wireless silicon development team in California.

You will perform pre-silicon RTL verification of the wireless MAC and its interfaces, build reusable test benches, and drive coverage and quality with metric-driven verification across DV methods. You will collaborate with DV methodologists, designers, and systems engineers to deploy the latest verification techniques, including AI-assisted debugging, and you will