Senior WiFi MAC DV Engineer - AI-Driven Verification

Apple, Inc.; Sunnyvale (CA); On-site; USD 185,000 - 325,000; Full time

Benefits offered by this job

Comprehensive medical and dental

Employee stock programs

Tuition reimbursement

Relocation assistance

Job summary

Apple, Inc. in Sunnyvale seeks a Wireless MAC Design Verification Engineer to drive verification of WIFI MAC blocks within the N1/SoC family. Architect test benches, develop environments, and integrate AI-assisted workflows to accelerate debugging and coverage closure.

You should bring hands-on experience across the full ASIC DV cycle, UVM-based methodologies, and strong SystemVerilog/OOP skills. Prior wireless MAC verification is a plus; relocation and comprehensive compensation are offered.

Qualifications

• BS and a minimum of 10 years relevant industry experience.
• Advanced knowledge of standard ASIC design and verification flows.
• Proven track record in leading the verification methodology for clusters, subsystems, or full-chip designs.
• Deep proficiency in OOP, SystemVerilog, UVM.

Responsibilities

• Own critical block and sub-system verification of WIFI MAC.
• Architect and develop test-benches, environments and define new verification methodologies.
• Leverage AI-based tools (such as Claude Code) to accelerate verification workflows, automate testbench development, and enhance productivity.
• Learn new most advanced protocols related to IEEE 802.11 Wireless LAN specification.
• Create, simulate and debug test scenarios.
• Lead regressions and issue tracking.
• Collaborate with Design, Systems, SW engineering teams to review specifications and architecture, extract features, and define verification plans.
• Drive coverage analysis and closure.

Skills

OOP

SystemVerilog

UVM

Problem solving

Education

Bachelor's degree in a relevant field

Tools

Claude Code

Job description

Apple, Inc. in Sunnyvale seeks a Wireless MAC Design Verification Engineer to drive verification of WIFI MAC blocks within the N1/SoC family. Architect test benches, develop environments, and integrate AI-assisted workflows to accelerate debugging and coverage closure.

You should bring hands-on experience across the full ASIC DV cycle, UVM-based methodologies, and strong SystemVerilog/OOP skills. Prior wireless MAC verification is a plus; relocation and comprehensive compensation are offered.