Wireless SoC DV Engineer: MAC/PHY Verification

Apple, Inc.; San Diego (CA); In loco; USD 123.000 - 214.000; Tempo pieno

Vantaggi offerti da questo lavoro

Medical and dental coverage

Retirement benefits

Apple stock program

Relocation assistance

Tuition reimbursement

Descrizione del lavoro

Apple is seeking a Wireless Design Verification Engineer in San Diego to lead pre-silicon RTL verification of wireless MAC interfaces within a cutting-edge SoC. You will collaborate with DV methodologists, designers, and systems engineers to deliver high-quality testbenches and reusable verification environments.

The role emphasizes metric-driven verification, coverage development, and advanced methodologies, with opportunities to work with Palladium/FPGA validation and AI-driven analysis.

Competenze

• Bachelor's degree required.
• Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
• Experience with ASIC verification flows including test bench development and coverage.

Mansioni

• Review MAC subsystem microarchitecture and create verification plan to achieve coverage targets.
• Build block/subsystem level testbenches and UVM libraries for reusable verification environments.
• Develop directed and constrained random tests, debug, and drive issue closure with designers.
• Create and analyze coverage models and add test cases to increase coverage.
• Use AI to identify design and test bench issues and improve DV quality.
• Support MAC validation using Palladium and/or FPGA.

Conoscenze

Verilog

SystemVerilog

UVM

SystemVerilog Assertion

Formazione

Bachelor's degree

Strumenti

Palladium

FPGA

Descrizione del lavoro

Apple is seeking a Wireless Design Verification Engineer in San Diego to lead pre-silicon RTL verification of wireless MAC interfaces within a cutting-edge SoC. You will collaborate with DV methodologists, designers, and systems engineers to deliver high-quality testbenches and reusable verification environments.

The role emphasizes metric-driven verification, coverage development, and advanced methodologies, with opportunities to work with Palladium/FPGA validation and AI-driven analysis.