Job summary
Cadence Design Systems is seeking a Principal Product Engineer for their Virtual Protocols Team in San Jose. The role involves developing and deploying cutting-edge verification technologies and working directly with customers. Candidates should have strong expertise in software, hardware, and protocols essential for SOC verification. A related degree is required alongside 5-7 years of experience. The position offers a competitive salary range of $136,500 to $253,500, incentive compensation, and comprehensive benefits.
Protocol knowledge (PCIe, CXL, Ethernet, USB, AMBA)
Verification Methodologies (UVM, SystemVerilog, Virtual Prototyping)
Software development (C/C++, Object Oriented programming)
SOC design and verification experience
Hardware emulation experience
HDL language knowledge (SystemVerilog, VHDL)
Scripting language knowledge (shell, python, perl)
Compiler tools (make, gcc/g++)
Bachelor's degree in Computer Science or Electrical Engineering
Master's degree in Computer Science or Electrical Engineering