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Benefits dieser Stelle
Comprehensive medical and dental coverage
Retirement benefits
Discounted products and free services
Educational reimbursement
Discretionary bonuses or commission payments
Relocation assistance
Zusammenfassung
A leading technology company in Cupertino is seeking an experienced professional to join its Emulation verification team. The role involves working on verifying large SoCs and collaborating with various teams. Ideal candidates should have at least 10 years of experience, a BS degree, and strong skills in SystemVerilog and verification environments. The position offers a competitive salary range of $181,100 to $318,400 along with comprehensive benefits, including stock purchase plans and educational reimbursements.
Qualifikationen
Minimum of BS + 10 years relevant industry experience.
Understanding of the tool flow from RTL to Emulation is a huge plus.
Good understanding of Standard Emulator (Palladium, Veloce, Zebu) or FPGA (Xilinx, Altera) flow.
Experience in writing Synthesize-able SystemVerilog/Verilog code and SystemVerilog assertions.
Experience with System Verilog verification environments including C/C++ DPI, UVM.
Experience with writing and debugging test FW.
Experience on any Scripting (Perl/Python/TCL).
Excellent analytical and debug skills.
Experience in UVM Acceleration is a plus.
Aufgaben
Collaborate closely with Architecture, Design, DV, Silicon Validation, Power, and SW teams.
Develop/apply synthesizable monitors/checkers, stimulus on emulation platform.
Prepare and complete the test plan and perform reviews with multi-functional teams.
Perform low power testing on emulation platform.
Develop code for Design and verification that aids emulation activities.
Jobbeschreibung
A leading technology company in Cupertino is seeking an experienced professional to join its Emulation verification team. The role involves working on verifying large SoCs and collaborating with various teams. Ideal candidates should have at least 10 years of experience, a BS degree, and strong skills in SystemVerilog and verification environments. The position offers a competitive salary range of $181,100 to $318,400 along with comprehensive benefits, including stock purchase plans and educational reimbursements.
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