Senior Verification Lead: SystemVerilog/UVM (Onsite)

Amaze Systems; Redmond (WA); On-site; USD 140,000 - 190,000; Full time

Job summary

A technology consulting firm in Redmond, WA is looking for a Design Verification Lead specializing in SystemVerilog and UVM. The ideal candidate will possess extensive experience in architecting and maintaining UVM testbenches and leading verification teams. Responsibilities include defining verification strategies and collaborating with design teams to ensure quality and efficiency in the silicon development process. This role is crucial for those with a deep understanding of AMBA protocols and a track record in hands-on verification and leadership. Full-time onsite position.

Qualifications

• 8+ years of hands-on Design Verification experience.
• Strong expertise in SystemVerilog and UVM.
• Proven experience in developing UVM testbenches from scratch.

Responsibilities

• Lead and execute IP/Module-level Design Verification using SystemVerilog and UVM.
• Architect, develop, and maintain UVM testbenches from scratch.
• Define and own verification strategies.

Skills

Design Verification

SystemVerilog

UVM

Debugging

Test Planning

Job description

A technology consulting firm in Redmond, WA is looking for a Design Verification Lead specializing in SystemVerilog and UVM. The ideal candidate will possess extensive experience in architecting and maintaining UVM testbenches and leading verification teams. Responsibilities include defining verification strategies and collaborating with design teams to ensure quality and efficiency in the silicon development process. This role is crucial for those with a deep understanding of AMBA protocols and a track record in hands-on verification and leadership. Full-time onsite position.