Senior UVM Verification Lead (SystemVerilog)

Artha Nexgen; Seattle (WA); On-site; USD 153,000 - 187,000; Full time

Job summary

Artha Nexgen is seeking a UVM Lead Verification Engineer in Seattle to lead a design verification team at a customer location. The role requires expertise in System Verilog and UVM, with a focus on developing UVM testbenches and managing a team.

Candidates should have 8 years of experience in the field with strong debugging skills. The position is full-time, offering a competitive salary of $170k annually.

Qualifications

• Lead Design Verification Team (minimum 5 members).
• Experience in porting existing Verilog/VHDL to UVM.
• Expertise in test planning, coverage coding and debugging.

Responsibilities

• Lead the team's verification efforts and debugging of verification environments.
• Develop test plans and coverage.

Skills

Design verification expertise in System Verilog / UVM

Strong background in developing UVM testbenches

Experience in VIP integration

Knowledge of AMBA protocol

Job description

Artha Nexgen is seeking a UVM Lead Verification Engineer in Seattle to lead a design verification team at a customer location. The role requires expertise in System Verilog and UVM, with a focus on developing UVM testbenches and managing a team.

Candidates should have 8 years of experience in the field with strong debugging skills. The position is full-time, offering a competitive salary of $170k annually.