UVM Lead Verification Engineer

Artha Nexgen; Seattle (WA); On-site; USD 153,000 - 187,000; Full time

Job summary

Artha Nexgen is seeking a UVM Lead Verification Engineer in Seattle to lead a design verification team at a customer location. The role requires expertise in System Verilog and UVM, with a focus on developing UVM testbenches and managing a team.

Candidates should have 8 years of experience in the field with strong debugging skills. The position is full-time, offering a competitive salary of $170k annually.

Qualifications

• Lead Design Verification Team (minimum 5 members).
• Experience in porting existing Verilog/VHDL to UVM.
• Expertise in test planning, coverage coding and debugging.

Responsibilities

• Lead the team's verification efforts and debugging of verification environments.
• Develop test plans and coverage.

Skills

Design verification expertise in System Verilog / UVM

Strong background in developing UVM testbenches

Experience in VIP integration

Knowledge of AMBA protocol

Job description

Job Description

Location: Redmond, Seattle, Washington

Experience: 8-15 years

Onsite: YES @ customer location

Duration: Long Term

Full time rate: $170k

Visa: USC and GC

Only local candidates please.

Qualifications

• Lead Design Verification Team (minimum 5 members)
• Design verification expertise in System Verilog / UVM for unit/module level verification
• Strong background in developing UVM testbenches from scratch
• Experience in VIP integration and bring up
• Porting existing Verilog/VHDL environment to UVM-based environment
• Experience in test planning, coverage coding and debugging
• Deep knowledge of AMBA protocol

Responsibilities

Lead the team's verification efforts, including test plan and coverage development, and debugging of verification environments.

Job Overview

Date Posted: 29-01-2026

Job Title: UVM Lead Verification Engineer

Work Experience: 8 years

Salary: USD $170k annually